mirror of
https://github.com/AsahiLinux/u-boot
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280 lines
7 KiB
C
280 lines
7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*/
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#include <common.h>
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#include <command.h>
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#include <cpu_func.h>
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#include <env.h>
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#include <init.h>
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#include <log.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <mvebu_mmc.h>
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void reset_cpu(void)
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{
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struct kwcpu_registers *cpureg =
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(struct kwcpu_registers *)KW_CPU_REG_BASE;
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writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
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&cpureg->rstoutn_mask);
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writel(readl(&cpureg->sys_soft_rst) | 1,
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&cpureg->sys_soft_rst);
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while (1) ;
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}
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/*
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* Window Size
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* Used with the Base register to set the address window size and location.
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* Must be programmed from LSB to MSB as sequence of ones followed by
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* sequence of zeros. The number of ones specifies the size of the window in
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* 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
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* NOTE: A value of 0x0 specifies 64-KByte size.
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*/
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unsigned int kw_winctrl_calcsize(unsigned int sizeval)
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{
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int i;
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unsigned int j = 0;
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u32 val = sizeval >> 1;
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for (i = 0; val >= 0x10000; i++) {
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j |= (1 << i);
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val = val >> 1;
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}
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return (0x0000ffff & j);
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}
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static const struct mbus_win windows[] = {
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/* Window 0: PCIE MEM address space */
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{ KW_DEFADR_PCI_MEM, KW_DEFADR_PCI_MEM_SIZE,
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KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM },
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/* Window 1: PCIE IO address space */
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{ KW_DEFADR_PCI_IO, KW_DEFADR_PCI_IO_SIZE,
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KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO },
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/* Window 2: NAND Flash address space */
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{ KW_DEFADR_NANDF, 1024 * 1024 * 128,
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KWCPU_TARGET_MEMORY, KWCPU_ATTR_NANDFLASH },
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/* Window 3: SPI Flash address space */
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{ KW_DEFADR_SPIF, 1024 * 1024 * 128,
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KWCPU_TARGET_MEMORY, KWCPU_ATTR_SPIFLASH },
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/* Window 4: BOOT Memory address space */
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{ KW_DEFADR_BOOTROM, 1024 * 1024 * 128,
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KWCPU_TARGET_MEMORY, KWCPU_ATTR_BOOTROM },
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/* Window 5: Security SRAM address space */
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{ KW_DEFADR_SASRAM, 1024 * 64,
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KWCPU_TARGET_SASRAM, KWCPU_ATTR_SASRAM },
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};
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/*
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* SYSRSTn Duration Counter Support
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*
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* Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
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* When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
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* The SYSRSTn duration counter is useful for implementing a manufacturer
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* or factory reset. Upon a long reset assertion that is greater than a
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* pre-configured environment variable value for sysrstdelay,
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* The counter value is stored in the SYSRSTn Length Counter Register
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* The counter is based on the 25-MHz reference clock (40ns)
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* It is a 29-bit counter, yielding a maximum counting duration of
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* 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
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* it remains at this value until counter reset is triggered by setting
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* bit 31 of KW_REG_SYSRST_CNT
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*/
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static void kw_sysrst_action(void)
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{
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int ret;
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char *s = env_get("sysrstcmd");
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if (!s) {
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debug("Error.. %s failed, check sysrstcmd\n",
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__FUNCTION__);
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return;
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}
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debug("Starting %s process...\n", __FUNCTION__);
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ret = run_command(s, 0);
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if (ret != 0)
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debug("Error.. %s failed\n", __FUNCTION__);
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else
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debug("%s process finished\n", __FUNCTION__);
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}
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static void kw_sysrst_check(void)
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{
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u32 sysrst_cnt, sysrst_dly;
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char *s;
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/*
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* no action if sysrstdelay environment variable is not defined
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*/
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s = env_get("sysrstdelay");
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if (s == NULL)
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return;
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/* read sysrstdelay value */
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sysrst_dly = (u32)dectoul(s, NULL);
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/* read SysRst Length counter register (bits 28:0) */
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sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
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debug("H/w Rst hold time: %d.%d secs\n",
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sysrst_cnt / SYSRST_CNT_1SEC_VAL,
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sysrst_cnt % SYSRST_CNT_1SEC_VAL);
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/* clear the counter for next valid read*/
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writel(1 << 31, KW_REG_SYSRST_CNT);
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/*
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* sysrst_action:
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* if H/w Reset key is pressed and hold for time
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* more than sysrst_dly in seconds
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*/
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if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
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kw_sysrst_action();
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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char *rev = "??";
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u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
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u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
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if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
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printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
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return -1;
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}
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switch (revid) {
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case 0:
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if (devid == 0x6281)
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rev = "Z0";
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else if (devid == 0x6282)
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rev = "A0";
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break;
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case 1:
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rev = "A1";
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break;
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case 2:
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rev = "A0";
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break;
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case 3:
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rev = "A1";
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break;
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default:
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break;
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}
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printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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#ifdef CONFIG_ARCH_CPU_INIT
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int arch_cpu_init(void)
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{
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u32 reg;
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struct kwcpu_registers *cpureg =
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(struct kwcpu_registers *)KW_CPU_REG_BASE;
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/* Linux expects the internal registers to be at 0xf1000000 */
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writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
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/* Enable and invalidate L2 cache in write through mode */
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writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
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invalidate_l2_cache();
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#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
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/*
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* Configures the I/O voltage of the pads connected to Egigabit
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* Ethernet interface to 1.8V
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* By default it is set to 3.3V
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*/
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reg = readl(KW_REG_MPP_OUT_DRV_REG);
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reg |= (1 << 7);
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writel(reg, KW_REG_MPP_OUT_DRV_REG);
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#endif
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#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
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/*
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* Set egiga port0/1 in normal functional mode
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* This is required becasue on kirkwood by default ports are in reset mode
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* OS egiga driver may not have provision to set them in normal mode
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* and if u-boot is build without network support, network may fail at OS level
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*/
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reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
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reg &= ~(1 << 4); /* Clear PortReset Bit */
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writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
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reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
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reg &= ~(1 << 4); /* Clear PortReset Bit */
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writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
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#endif
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#ifdef CONFIG_KIRKWOOD_PCIE_INIT
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/*
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* Enable PCI Express Port0
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*/
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reg = readl(&cpureg->ctrl_stat);
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reg |= (1 << 0); /* Set PEX0En Bit */
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writel(reg, &cpureg->ctrl_stat);
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#endif
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return 0;
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}
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#endif /* CONFIG_ARCH_CPU_INIT */
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/*
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* SOC specific misc init
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*/
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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volatile u32 temp;
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/*CPU streaming & write allocate */
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temp = readfr_extra_feature_reg();
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temp &= ~(1 << 28); /* disable wr alloc */
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writefr_extra_feature_reg(temp);
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temp = readfr_extra_feature_reg();
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temp &= ~(1 << 29); /* streaming disabled */
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writefr_extra_feature_reg(temp);
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/* L2Cache settings */
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temp = readfr_extra_feature_reg();
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/* Disable L2C pre fetch - Set bit 24 */
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temp |= (1 << 24);
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/* enable L2C - Set bit 22 */
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temp |= (1 << 22);
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writefr_extra_feature_reg(temp);
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/* Change reset vector to address 0x0 */
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temp = get_cr();
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set_cr(temp & ~CR_V);
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/* Configure mbus windows */
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mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
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/* checks and execute resset to factory event */
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kw_sysrst_check();
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return 0;
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}
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#endif /* CONFIG_ARCH_MISC_INIT */
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#ifdef CONFIG_MVGBE
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int cpu_eth_init(struct bd_info *bis)
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{
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mvgbe_initialize(bis);
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return 0;
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}
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#endif
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