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u-boot/arch/riscv/lib
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Rick Chen a1f24875c3 riscv: Add a SYSCON driver for Andestech's PLMT 
The platform-Level Machine Timer (PLMT) block
holds memory-mapped mtime register associated
with timer tick.

This driver implements the riscv_get_time() which
is required by the generic RISC-V timer driver.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-08 09:45:08 +08:00
..
andes_plic.c riscv: Add a SYSCON driver for Andestech's PLIC 2019-04-08 09:45:08 +08:00
andes_plmt.c riscv: Add a SYSCON driver for Andestech's PLMT 2019-04-08 09:45:08 +08:00
asm-offsets.c riscv: add support for multi-hart systems 2019-04-08 09:44:26 +08:00
boot.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
bootm.c riscv: boot images passed to bootm on all harts 2019-04-08 09:44:26 +08:00
cache.c riscv: use invalidate/flush_*cache_range functions in cache.c 2019-01-15 09:36:31 +08:00
crt0_riscv_efi.S riscv: efi: Generate Microsoft PE format compliant images 2018-12-02 21:59:36 +01:00
elf_riscv32_efi.lds SPDX: Convert single license tags to Linux Kernel style 2018-05-29 14:44:21 +08:00
elf_riscv64_efi.lds SPDX: Convert single license tags to Linux Kernel style 2018-05-29 14:44:21 +08:00
interrupts.c riscv: clarify error message on undefined exceptions 2019-01-15 09:36:31 +08:00
Makefile riscv: Add a SYSCON driver for Andestech's PLMT 2019-04-08 09:45:08 +08:00
rdtime.c riscv: Implement riscv_get_time() API using rdtime instruction 2018-12-18 09:56:27 +08:00
reloc_riscv_efi.c riscv: Remove unused _relocate arguments 2018-07-19 16:31:37 -04:00
reset.c riscv: cosmetic: Reword do_reset() printf message. 2018-10-03 17:49:27 +08:00
sbi_ipi.c riscv: implement IPI platform functions using SBI 2019-04-08 09:44:26 +08:00
setjmp.S riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I 2018-11-26 13:57:29 +08:00
sifive_clint.c riscv: Add a SYSCON driver for SiFive's Core Local Interruptor 2018-12-18 09:56:26 +08:00
smp.c riscv: add infrastructure for calling functions on other harts 2019-04-08 09:44:25 +08:00