mirror of
https://github.com/AsahiLinux/u-boot
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61290fb52c
QCA9563 is CPU used on AP152 board :
Clock speed : 750 MHz ,
Arch : Mips 74Kc,
Eth : SGMII interface,
MIMO config : 3 * 3 450M,
2 * USB 2.0,
Signed-off-by: Rosy Song <rosysong@rosinson.com>
Changes for v2:
- coding style cleanup
- remove ununsed flash chip in defconfig
- enable automatic icache / dcache size in defconfig
Changes for v3:
- add detailed information for qca956x in commit message
Changes for v4:
- remove pre-configured network settings in ap152.h
Changes for v5:
- coding style cleanup
193 lines
4.2 KiB
ArmAsm
193 lines
4.2 KiB
ArmAsm
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
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*
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* Based on QSDK
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*/
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#include <config.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <mach/ar71xx_regs.h>
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.set noreorder
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LEAF(ddr_tap_tuning)
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li a0, 0xbd001f00
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sw zero, 0x0(a0) /* Place where the tap values are saved and used for SWEEP */
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sw zero, 0x4(a0) /* Place where the number of passing taps are saved. */
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sw zero, 0x14(a0) /* Place where the last pass tap value is stored */
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li a1, 0xaa55aa55 /* Indicates that the First pass tap value is not found */
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sw a1, 0x10(a0) /* Place where the First pass tap value is stored */
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nop
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li a0, CKSEG1ADDR(AR71XX_RESET_BASE) /* RESET_BASE_ADDRESS */
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lw a1, 0x1c(a0) /* Reading the RST_RESET_ADDRESS */
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li a2, 0x08000000 /* Setting the RST_RESET_RTC_RESET */
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or a1, a1, a2
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sw a1, 0x1c(a0)
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li a3, 0xffffffff
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xor a2, a2, a3
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and a1, a1, a2
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sw a1, 0x1c(a0) /* Taking the RTC out of RESET */
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nop
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li a0, CKSEG1ADDR(QCA956X_RTC_BASE) /* RTC_BASE_ADDRESS */
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li a1, 0x1
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sw a1, 0x0040(a0) /* RTC_SYNC_RESET_ADDRESS */
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li a2, 0x2
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_poll_for_RTC_ON:
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lw a1, 0x0044(a0) /* RTC_SYNC_STATUS_ADDRESS */
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and a1, a2, a1
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bne a1, a2, _poll_for_RTC_ON
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nop
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_CHANGE_TAPS:
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li t0, 0xbd001f00 /* Read the current value of the TAP for programming */
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lw t1, 0x0(t0)
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li t2, 0x00000000
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or t3, t1, t2
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li t0, 0xb8000000 /* DDR_BASE_ADDRESS */
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sw t3, 0x1c(t0) /* TAP_CONTROL_0_ADDRESS */
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sw t3, 0x20(t0) /* TAP_CONTROL_1_ADDRESS */
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sw t3, 0x24(t0) /* TAP_CONTROL_2_ADDRESS */
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sw t3, 0x28(t0) /* TAP_CONTROL_3_ADDRESS */
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li t1, 0x00000010 /* Running the test 8 times */
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sw t1, 0x0068(t0) /* PERF_COMP_ADDR_1_ADDRESS */
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li t1, 0xfa5de83f /* 4 Row Address Bits, 4 Column Address Bits, 2 BA bits */
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sw t1, 0x002c(t0) /* PERF_MASK_ADDR_0_ADDRESS */
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li t1, 0x0000ffff
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sw t1, 0x0070(t0) /* PERF_COMP_AHB_GE0_1_ADDRESS */
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li t1, 0x0000ffff
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sw t1, 0x0040(t0) /* PERF_COMP_AHB_GE1_0_ADDRESS */
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li t1, 0x0000ffff
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sw t1, 0x0078(t0) /* PERF_COMP_AHB_GE1_1_ADDRESS */
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li t1, 0x0000ffff
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sw t1, 0x0034(t0) /* PERF_MASK_AHB_GE0_0_ADDRESS */
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li t1, 0x0000ffff
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sw t1, 0x006c(t0) /* PERF_MASK_AHB_GE0_1_ADDRESS */
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li t1, 0x0000ffff
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sw t1, 0x003c(t0) /* PERF_MASK_AHB_GE1_0_ADDRESS */
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li t1, 0x0000ffff
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sw t1, 0x0074(t0) /* PERF_MASK_AHB_GE1_1_ADDRESS */
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li t1, 0x0000ffff
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sw t1, 0x0038(t0) /* PERF_COMP_AHB_GE0_0_ADDRESS */
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li t1, 0x00000001
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sw t1, 0x011c(t0) /* DDR_BIST_ADDRESS */
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li t2, 0x1
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_bist_done_poll:
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lw t1, 0x0120(t0) /* DDR_BIST_STATUS_ADDRESS */
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and t1, t1, t2
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bne t1, t2, _bist_done_poll
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nop
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lw t1, 0x0120(t0) /* DDR_BIST_STATUS_ADDRESS */
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li t4, 0x000001fe
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and t2, t1, t4
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srl t2, t2, 0x1 /* no. of Pass Runs */
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li t5, 0x00000000
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sw t5, 0x011c(t0) /* DDR_BIST_ADDRESS - Stop the DDR BIST test */
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li t5, 0x0001fe00
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and t5, t5, t1
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bnez t5, _iterate_tap /* This is a redundant compare but nevertheless - Comparing the FAILS */
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nop
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lw t1, 0x0068(t0) /* PERF_COMP_ADDR_1_ADDRESS */
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li t3, 0x000001fe
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and t3, t3, t1
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srl t3, t3, 0x1 /* No. of runs in the config register. */
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bne t3, t2, _iterate_tap
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nop
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pass_tap:
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li t0, 0xbd001f00
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lw t1, 0x4(t0)
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addiu t1, t1, 0x1
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sw t1, 0x4(t0)
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li t0, 0xbd001f10
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lw t1, 0x0(t0)
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li t2, 0xaa55aa55
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beq t1, t2, _first_pass
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nop
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li t0, 0xbd001f00
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lw t1, 0x0(t0)
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li t0, 0xbd001f10
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sw t1, 0x4(t0)
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nop
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b _iterate_tap
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nop
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_first_pass:
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li t0, 0xbd001f00
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lw t1, 0x0(t0)
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li t0, 0xbd001f10
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sw t1, 0x0(t0)
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sw t1, 0x4(t0)
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nop
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_iterate_tap:
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li t0, 0xbd001f00
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lw t1, 0x0(t0)
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li t2, 0x3f
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beq t1, t2, _STOP_TEST
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nop
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addiu t1, t1, 0x1
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sw t1, 0x0(t0)
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nop
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b _CHANGE_TAPS
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nop
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_STOP_TEST:
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li t0, 0xbd001f00
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lw t1, 0x4(t0)
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bnez t1, _load_center_tap
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nop
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li t3, 0x8 /* Default Tap to be used */
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b _load_tap_into_reg
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nop
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_load_center_tap:
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li t0, 0xbd001f10
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lw t1, 0x0(t0)
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lw t2, 0x4(t0)
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add t3, t1, t2
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srl t3, t3, 0x1
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li t4, 0x3f
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and t3, t3, t4
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_load_tap_into_reg:
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li t0, 0xb8000000
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sw t3, 0x1c(t0) /* TAP_CONTROL_0_ADDRESS */
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sw t3, 0x20(t0) /* TAP_CONTROL_1_ADDRESS */
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sw t3, 0x24(t0) /* TAP_CONTROL_2_ADDRESS */
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sw t3, 0x28(t0) /* TAP_CONTROL_3_ADDRESS */
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nop
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jr ra
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nop
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END(ddr_tap_tuning)
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