u-boot/doc/device-tree-bindings/misc/cros-ec.txt
Hung-ying Tyan 88364387c6 cros: add cros_ec driver
This patch adds the cros_ec driver that implements the protocol for
communicating with Google's ChromeOS embedded controller.

Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:07:11 -04:00

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Chrome OS CROS_EC Binding
======================
The device tree node which describes the operation of the CROS_EC interface
is as follows:
Required properties :
- compatible = "google,cros-ec"
Optional properties :
- spi-max-frequency : Sets the maximum frequency (in Hz) for SPI bus
operation
- i2c-max-frequency : Sets the maximum frequency (in Hz) for I2C bus
operation
- ec-interrupt : Selects the EC interrupt, defined as a GPIO according
to the platform
- optimise-flash-write : Boolean property - if present then flash blocks
containing all 0xff will not be written, since we assume that the EC
uses that pattern for erased blocks
The CROS_EC node should appear as a subnode of the interrupt that connects it
to the EC (e.g. i2c, spi, lpc). The reg property (as usual) will indicate
the unit address on that bus.
Example
=======
spi@131b0000 {
cros-ec@0 {
reg = <0>;
compatible = "google,cros-ec";
spi-max-frequency = <5000000>;
ec-interrupt = <&gpio 174 1>;
optimise-flash-write;
status = "disabled";
};
};