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https://github.com/AsahiLinux/u-boot
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1e94b46f73
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
312 lines
6.5 KiB
C
312 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
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*/
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#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
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#include <common.h>
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#include <errno.h>
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#include <log.h>
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#include <linux/printk.h>
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#include "xusb-padctl-common.h"
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#include <asm/arch/clock.h>
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int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
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{
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if (phy && phy->ops && phy->ops->prepare)
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return phy->ops->prepare(phy);
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return phy ? -ENOSYS : -EINVAL;
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}
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int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
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{
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if (phy && phy->ops && phy->ops->enable)
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return phy->ops->enable(phy);
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return phy ? -ENOSYS : -EINVAL;
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}
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int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
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{
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if (phy && phy->ops && phy->ops->disable)
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return phy->ops->disable(phy);
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return phy ? -ENOSYS : -EINVAL;
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}
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int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
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{
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if (phy && phy->ops && phy->ops->unprepare)
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return phy->ops->unprepare(phy);
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return phy ? -ENOSYS : -EINVAL;
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}
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struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
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{
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struct tegra_xusb_phy *phy;
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int i;
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for (i = 0; i < padctl.socdata->num_phys; i++) {
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phy = &padctl.socdata->phys[i];
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if (phy->type != type)
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continue;
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return phy;
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}
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return NULL;
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}
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static const struct tegra_xusb_padctl_lane *
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tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
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{
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unsigned int i;
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for (i = 0; i < padctl->socdata->num_lanes; i++)
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if (strcmp(name, padctl->socdata->lanes[i].name) == 0)
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return &padctl->socdata->lanes[i];
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return NULL;
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}
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static int
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tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
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struct tegra_xusb_padctl_group *group,
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ofnode node)
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{
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unsigned int i;
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int len, ret;
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group->name = ofnode_get_name(node);
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len = ofnode_read_string_count(node, "nvidia,lanes");
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if (len < 0) {
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pr_err("failed to parse \"nvidia,lanes\" property\n");
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return -EINVAL;
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}
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group->num_pins = len;
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for (i = 0; i < group->num_pins; i++) {
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ret = ofnode_read_string_index(node, "nvidia,lanes", i,
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&group->pins[i]);
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if (ret) {
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pr_err("failed to read string from \"nvidia,lanes\" property\n");
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return -EINVAL;
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}
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}
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group->num_pins = len;
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ret = ofnode_read_string_index(node, "nvidia,function", 0,
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&group->func);
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if (ret) {
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pr_err("failed to parse \"nvidia,func\" property\n");
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return -EINVAL;
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}
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group->iddq = ofnode_read_u32_default(node, "nvidia,iddq", -1);
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return 0;
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}
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static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
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const char *name)
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{
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unsigned int i;
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for (i = 0; i < padctl->socdata->num_functions; i++)
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if (strcmp(name, padctl->socdata->functions[i]) == 0)
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return i;
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return -ENOENT;
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}
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static int
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tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
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const struct tegra_xusb_padctl_lane *lane,
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const char *name)
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{
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unsigned int i;
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int func;
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func = tegra_xusb_padctl_find_function(padctl, name);
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if (func < 0)
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return func;
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for (i = 0; i < lane->num_funcs; i++)
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if (lane->funcs[i] == func)
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return i;
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return -ENOENT;
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}
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static int
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tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
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const struct tegra_xusb_padctl_group *group)
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{
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unsigned int i;
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for (i = 0; i < group->num_pins; i++) {
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const struct tegra_xusb_padctl_lane *lane;
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unsigned int func;
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u32 value;
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lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
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if (!lane) {
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pr_err("no lane for pin %s", group->pins[i]);
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continue;
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}
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func = tegra_xusb_padctl_lane_find_function(padctl, lane,
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group->func);
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if (func < 0) {
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pr_err("function %s invalid for lane %s: %d",
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group->func, lane->name, func);
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continue;
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}
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value = padctl_readl(padctl, lane->offset);
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/* set pin function */
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value &= ~(lane->mask << lane->shift);
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value |= func << lane->shift;
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/*
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* Set IDDQ if supported on the lane and specified in the
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* configuration.
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*/
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if (lane->iddq > 0 && group->iddq >= 0) {
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if (group->iddq != 0)
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value &= ~(1 << lane->iddq);
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else
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value |= 1 << lane->iddq;
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}
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padctl_writel(padctl, value, lane->offset);
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}
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return 0;
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}
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static int
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tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
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struct tegra_xusb_padctl_config *config)
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{
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unsigned int i;
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for (i = 0; i < config->num_groups; i++) {
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const struct tegra_xusb_padctl_group *group;
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int err;
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group = &config->groups[i];
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err = tegra_xusb_padctl_group_apply(padctl, group);
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if (err < 0) {
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pr_err("failed to apply group %s: %d",
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group->name, err);
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continue;
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}
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}
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return 0;
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}
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static int
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tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
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struct tegra_xusb_padctl_config *config,
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ofnode node)
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{
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ofnode subnode;
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config->name = ofnode_get_name(node);
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ofnode_for_each_subnode(subnode, node) {
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struct tegra_xusb_padctl_group *group;
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int err;
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group = &config->groups[config->num_groups];
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err = tegra_xusb_padctl_group_parse_dt(padctl, group, subnode);
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if (err < 0) {
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pr_err("failed to parse group %s\n", group->name);
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return err;
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}
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config->num_groups++;
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}
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return 0;
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}
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static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
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ofnode node)
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{
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ofnode subnode;
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int err;
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err = ofnode_read_resource(node, 0, &padctl->regs);
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if (err < 0) {
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pr_err("registers not found");
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return err;
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}
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ofnode_for_each_subnode(subnode, node) {
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struct tegra_xusb_padctl_config *config = &padctl->config;
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debug("%s: subnode=%s\n", __func__, ofnode_get_name(subnode));
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err = tegra_xusb_padctl_config_parse_dt(padctl, config,
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subnode);
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if (err < 0) {
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pr_err("failed to parse entry %s: %d\n",
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config->name, err);
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continue;
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}
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}
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debug("%s: done\n", __func__);
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return 0;
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}
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struct tegra_xusb_padctl padctl;
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int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
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const struct tegra_xusb_padctl_soc *socdata)
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{
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unsigned int i;
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int err;
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debug("%s: count=%d\n", __func__, count);
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for (i = 0; i < count; i++) {
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debug("%s: i=%d, node=%p\n", __func__, i, nodes[i].np);
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if (!ofnode_is_enabled(nodes[i]))
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continue;
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padctl.socdata = socdata;
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err = tegra_xusb_padctl_parse_dt(&padctl, nodes[i]);
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if (err < 0) {
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pr_err("failed to parse DT: %d\n", err);
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continue;
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}
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/* deassert XUSB padctl reset */
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reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
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err = tegra_xusb_padctl_config_apply(&padctl, &padctl.config);
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if (err < 0) {
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pr_err("failed to apply pinmux: %d", err);
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continue;
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}
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/* only a single instance is supported */
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break;
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}
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debug("%s: done\n", __func__);
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return 0;
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}
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