mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
1170d2b759
There have been some updates to the device trees, so re-sync. Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com>
285 lines
6.3 KiB
Text
285 lines
6.3 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
/*
|
|
* Copyright 2020 Compass Electronics Group, LLC
|
|
*/
|
|
|
|
/ {
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
led0 {
|
|
label = "gen_led0";
|
|
gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
|
|
default-state = "off";
|
|
};
|
|
|
|
led1 {
|
|
label = "gen_led1";
|
|
gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
|
|
default-state = "off";
|
|
};
|
|
|
|
led2 {
|
|
label = "gen_led2";
|
|
gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
|
|
default-state = "off";
|
|
};
|
|
|
|
led3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_led3>;
|
|
label = "heartbeat";
|
|
gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
|
|
linux,default-trigger = "heartbeat";
|
|
};
|
|
};
|
|
|
|
reg_audio: regulator-audio {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "3v3_aud";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
};
|
|
|
|
reg_usdhc2_vmmc: regulator-usdhc2 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "VSD_3V3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
};
|
|
|
|
sound {
|
|
compatible = "fsl,imx-audio-wm8962";
|
|
model = "wm8962-audio";
|
|
audio-cpu = <&sai3>;
|
|
audio-codec = <&wm8962>;
|
|
audio-routing =
|
|
"Headphone Jack", "HPOUTL",
|
|
"Headphone Jack", "HPOUTR",
|
|
"Ext Spk", "SPKOUTL",
|
|
"Ext Spk", "SPKOUTR",
|
|
"AMIC", "MICBIAS",
|
|
"IN3R", "AMIC";
|
|
};
|
|
};
|
|
|
|
&ecspi2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_espi2>;
|
|
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
|
|
eeprom@0 {
|
|
compatible = "microchip,at25160bn", "atmel,at25";
|
|
reg = <0>;
|
|
spi-max-frequency = <5000000>;
|
|
spi-cpha;
|
|
spi-cpol;
|
|
pagesize = <32>;
|
|
size = <2048>;
|
|
address-width = <16>;
|
|
};
|
|
};
|
|
|
|
&i2c2 {
|
|
clock-frequency = <400000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c2>;
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c4 {
|
|
clock-frequency = <400000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c4>;
|
|
status = "okay";
|
|
|
|
wm8962: audio-codec@1a {
|
|
compatible = "wlf,wm8962";
|
|
reg = <0x1a>;
|
|
clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
|
|
clock-names = "xclk";
|
|
DCVDD-supply = <®_audio>;
|
|
DBVDD-supply = <®_audio>;
|
|
AVDD-supply = <®_audio>;
|
|
CPVDD-supply = <®_audio>;
|
|
MICVDD-supply = <®_audio>;
|
|
PLLVDD-supply = <®_audio>;
|
|
SPKVDD1-supply = <®_audio>;
|
|
SPKVDD2-supply = <®_audio>;
|
|
gpio-cfg = <
|
|
0x0000 /* 0:Default */
|
|
0x0000 /* 1:Default */
|
|
0x0000 /* 2:FN_DMICCLK */
|
|
0x0000 /* 3:Default */
|
|
0x0000 /* 4:FN_DMICCDAT */
|
|
0x0000 /* 5:Default */
|
|
>;
|
|
};
|
|
|
|
pca6416_0: gpio@20 {
|
|
compatible = "nxp,pcal6416";
|
|
reg = <0x20>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pcal6414>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-parent = <&gpio4>;
|
|
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
pca6416_1: gpio@21 {
|
|
compatible = "nxp,pcal6416";
|
|
reg = <0x21>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-parent = <&gpio4>;
|
|
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
};
|
|
|
|
&sai3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_sai3>;
|
|
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
|
|
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
|
|
assigned-clock-rates = <24576000>;
|
|
fsl,sai-mclk-direction-output;
|
|
status = "okay";
|
|
};
|
|
|
|
&snvs_pwrkey {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart2 { /* console */
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart3>;
|
|
assigned-clocks = <&clk IMX8MM_CLK_UART3>;
|
|
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc2 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
|
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
|
|
bus-width = <4>;
|
|
vmmc-supply = <®_usdhc2_vmmc>;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl_espi2: espi2grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
|
|
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
|
|
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
|
|
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
|
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c4: i2c4grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
|
|
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_led3: led3grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41
|
|
>;
|
|
};
|
|
|
|
pinctrl_pcal6414: pcal6414-gpiogrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai3: sai3grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
|
|
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
|
|
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
|
|
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
|
|
MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
|
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3: uart3grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
|
|
MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
|
|
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
|
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
|
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
|
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
|
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
|
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
|
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
|
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
|
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
|
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
|
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
|
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
|
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
|
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
|
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
|
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
|
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
|
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
|
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
|
>;
|
|
};
|
|
};
|