Alexey Brodkin 6eb15e50f4 arc: add support for SLC (System Level Cache, AKA L2-cache) ... ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache). This change adds functions required for controlling SLC: * slc_enable/disable * slc_flush/invalidate For now we just disable SLC to escape DMA coherency issues until either: * SLC flush/invalidate is supported in DMA APIin U-Boot * hardware DMA coherency is implemented (that might be board specific so probably we'll need to have a separate Kconfig option for controlling SLC explicitly) Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>		2015-04-03 09:47:50 +03:00
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cpu	arc: merge common start-up code between ARC and ARCv2	2015-04-03 09:47:49 +03:00
dts	board: Switch Abilis TB-100 board to Driver Model for serial port	2015-04-03 09:47:49 +03:00
include/asm	arc: add support for SLC (System Level Cache, AKA L2-cache)	2015-04-03 09:47:50 +03:00
lib	arc: add support for SLC (System Level Cache, AKA L2-cache)	2015-04-03 09:47:50 +03:00
config.mk	generic-board: move __HAVE_ARCH_GENERIC_BOARD to Kconfig	2015-03-28 09:03:08 -04:00
Kconfig	arc: minor fixes in Kconfig	2015-04-03 09:47:49 +03:00
Makefile	arc: introduce separate section for interrupt vector table	2015-01-15 22:38:42 +03:00