Siva Durga Prasad Paladugu 26e054c943 arm64: versal: fpga: Add PL bit stream load support ... This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>		2019-10-08 09:11:14 +02:00
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bootscripts	xilinx: Add sd boot command script for reference	2019-10-08 09:11:13 +02:00
common	xilinx: common: Remove !DM_i2C code for reading mac from eeprom	2019-02-14 14:31:10 +01:00
microblaze-generic	watchdog: Implement generic watchdog_reset() version	2019-04-26 09:16:32 +02:00
versal	arm64: versal: fpga: Add PL bit stream load support	2019-10-08 09:11:14 +02:00
zynq	env: Move env_set() to env.h	2019-08-11 16:43:41 -04:00
zynqmp	env: Move env_set() to env.h	2019-08-11 16:43:41 -04:00
zynqmp_r5	lib: fdtdec: Rename routine fdtdec_setup_memory_size()	2018-07-19 10:49:56 +02:00
Kconfig	arm/arm64: zynq/zynqmp: pass the PS init file as a kconfig variable	2018-07-19 10:49:53 +02:00