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e49cdbe10b
This patch adds support for running RX training using new command called "rx_training" Usage: rx_training - rx_training <cp id> <comphy id> RX training allows to improve link quality (for SFI mode) by running training sequence between us and the link partner, this allows to reach better link quality then using static configuration. Change-Id: I818fe67ccaf19a87af50d4c34a9db7d6802049a5 Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
194 lines
5.5 KiB
C
194 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015-2016 Marvell International Ltd.
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*/
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#ifndef _COMPHY_CORE_H_
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#define _COMPHY_CORE_H_
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#include <fdtdec.h>
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#include <mvebu/comphy.h>
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#if defined(DEBUG)
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#define debug_enter() printf("----> Enter %s\n", __func__);
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#define debug_exit() printf("<---- Exit %s\n", __func__);
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#else
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#define debug_enter()
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#define debug_exit()
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#endif
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/* COMPHY registers */
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#define COMMON_PHY_CFG1_REG 0x0
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#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
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#define COMMON_PHY_CFG1_PWR_UP_MASK \
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(0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
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#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
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#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \
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(0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
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#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13
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#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \
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(0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
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#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14
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#define COMMON_PHY_CFG1_CORE_RSTN_MASK \
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(0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
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#define COMMON_PHY_PHY_MODE_OFFSET 15
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#define COMMON_PHY_PHY_MODE_MASK \
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(0x1 << COMMON_PHY_PHY_MODE_OFFSET)
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#define COMMON_PHY_CFG6_REG 0x14
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#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
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#define COMMON_PHY_CFG6_IF_40_SEL_MASK \
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(0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
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#define COMMON_SELECTOR_PHY_OFFSET 0x140
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#define COMMON_SELECTOR_PIPE_OFFSET 0x144
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#define COMMON_PHY_SD_CTRL1 0x148
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#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
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#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
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#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
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#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \
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(0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
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#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
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#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \
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(0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
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#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
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#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \
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(0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
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#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
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#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
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(0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
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/* ToDo: Get this address via DT */
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#define MVEBU_CP0_REGS_BASE 0xF2000000UL
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#define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280)
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#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
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#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
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(0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
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#define MAX_LANE_OPTIONS 10
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#define MAX_UTMI_PHY_COUNT 3
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struct comphy_mux_options {
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u32 type;
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u32 mux_value;
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};
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struct comphy_mux_data {
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u32 max_lane_values;
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struct comphy_mux_options mux_values[MAX_LANE_OPTIONS];
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};
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struct chip_serdes_phy_config {
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struct comphy_mux_data *mux_data;
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int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
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struct comphy_map *);
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int (*rx_training)(struct chip_serdes_phy_config *, u32);
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void __iomem *comphy_base_addr;
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void __iomem *hpipe3_base_addr;
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u32 comphy_lanes_count;
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u32 comphy_mux_bitcount;
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const fdt32_t *comphy_mux_lane_order;
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u32 cp_index;
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struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
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};
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/* Register helper functions */
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static inline void reg_set_silent(void __iomem *addr, u32 data, u32 mask)
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{
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u32 reg_data;
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reg_data = readl(addr);
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reg_data &= ~mask;
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reg_data |= data;
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writel(reg_data, addr);
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}
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static inline void reg_set(void __iomem *addr, u32 data, u32 mask)
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{
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debug("Write to address = %#010lx, data = %#010x (mask = %#010x) - ",
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(unsigned long)addr, data, mask);
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debug("old value = %#010x ==> ", readl(addr));
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reg_set_silent(addr, data, mask);
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debug("new value %#010x\n", readl(addr));
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}
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static inline void reg_set_silent16(void __iomem *addr, u16 data, u16 mask)
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{
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u16 reg_data;
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reg_data = readw(addr);
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reg_data &= ~mask;
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reg_data |= data;
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writew(reg_data, addr);
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}
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static inline void reg_set16(void __iomem *addr, u16 data, u16 mask)
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{
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debug("Write to address = %#010lx, data = %#06x (mask = %#06x) - ",
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(unsigned long)addr, data, mask);
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debug("old value = %#06x ==> ", readw(addr));
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reg_set_silent16(addr, data, mask);
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debug("new value %#06x\n", readw(addr));
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}
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/* SoC specific init functions */
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#ifdef CONFIG_ARMADA_3700
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int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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struct comphy_map *serdes_map);
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#else
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static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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struct comphy_map *serdes_map)
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{
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/*
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* This function should never be called in this configuration, so
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* lets return an error here.
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*/
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return -1;
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}
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#endif
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#ifdef CONFIG_ARMADA_8K
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int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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struct comphy_map *serdes_map);
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int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
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u32 lane);
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#else
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static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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struct comphy_map *serdes_map)
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{
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/*
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* This function should never be called in this configuration, so
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* lets return an error here.
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*/
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return -1;
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}
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static inline int comphy_cp110_sfi_rx_training(
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struct chip_serdes_phy_config *ptr_chip_cfg,
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u32 lane)
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{
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/*
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* This function should never be called in this configuration, so
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* lets return an error here.
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*/
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return -1;
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}
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#endif
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void comphy_dedicated_phys_init(void);
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/* MUX function */
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void comphy_mux_init(struct chip_serdes_phy_config *ptr_chip_cfg,
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struct comphy_map *comphy_map_data,
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void __iomem *selector_base);
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void comphy_pcie_config_set(u32 comphy_max_count,
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struct comphy_map *serdes_map);
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void comphy_pcie_config_detect(u32 comphy_max_count,
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struct comphy_map *serdes_map);
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void comphy_pcie_unit_general_config(u32 pex_index);
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#endif /* _COMPHY_CORE_H_ */
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