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982a3c410e
The i.MX6 common timer uses the 32-bit variable tbl (time base lower) to record the overflow of the 32-bit counter. I.e. if the counter overflows, the variable tbl does overflow, too. To capture this overflow, use the variable tbu (time base upper), too. Return the combined value of tbl and tbu. lastinc is unused then, remove it. Signed-off-by: Knut Wohlrab <knut.wohlrab@de.bosch.com> Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de>
137 lines
3.3 KiB
C
137 lines
3.3 KiB
C
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <div64.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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/* General purpose timers registers */
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struct mxc_gpt {
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unsigned int control;
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unsigned int prescaler;
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unsigned int status;
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unsigned int nouse[6];
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unsigned int counter;
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};
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static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
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/* General purpose timers bitfields */
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#define GPTCR_SWR (1 << 15) /* Software reset */
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#define GPTCR_FRR (1 << 9) /* Freerun / restart */
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#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
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#define GPTCR_TEN 1 /* Timer enable */
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DECLARE_GLOBAL_DATA_PTR;
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static inline unsigned long long tick_to_time(unsigned long long tick)
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{
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tick *= CONFIG_SYS_HZ;
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do_div(tick, MXC_CLK32);
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return tick;
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}
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static inline unsigned long long us_to_tick(unsigned long long usec)
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{
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usec = usec * MXC_CLK32 + 999999;
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do_div(usec, 1000000);
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return usec;
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}
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int timer_init(void)
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{
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int i;
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/* setup GP Timer 1 */
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__raw_writel(GPTCR_SWR, &cur_gpt->control);
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/* We have no udelay by now */
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for (i = 0; i < 100; i++)
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__raw_writel(0, &cur_gpt->control);
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__raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
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/* Freerun Mode, PERCLK1 input */
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i = __raw_readl(&cur_gpt->control);
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__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
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gd->arch.tbl = __raw_readl(&cur_gpt->counter);
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gd->arch.tbu = 0;
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return 0;
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}
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unsigned long long get_ticks(void)
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{
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ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */
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/* increment tbu if tbl has rolled over */
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if (now < gd->arch.tbl)
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gd->arch.tbu++;
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gd->arch.tbl = now;
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return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
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}
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ulong get_timer_masked(void)
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{
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/*
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* get_ticks() returns a long long (64 bit), it wraps in
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* 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
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* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
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* 5 * 10^6 days - long enough.
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*/
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return tick_to_time(get_ticks());
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}
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ulong get_timer(ulong base)
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{
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return get_timer_masked() - base;
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}
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/* delay x useconds AND preserve advance timstamp value */
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void __udelay(unsigned long usec)
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{
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unsigned long long tmp;
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ulong tmo;
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tmo = us_to_tick(usec);
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tmp = get_ticks() + tmo; /* get current timestamp */
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while (get_ticks() < tmp) /* loop till event */
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/*NOP*/;
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return MXC_CLK32;
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}
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