u-boot/arch/arm/mach-imx/imx8m/soc.c
Peng Fan 9e09445549 imx8m: imx8mq: get chip rev for B1 revision
The i.MX8MQ B1 uses OCOTP_HW_OCOTP_READ_FUSE_DATA register for chip id.
It returns a magic number 0xff0055aa. update get_cpu_rev to support it,
and enable ocotp clock to access ocotp.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03 17:04:16 +01:00

345 lines
7.7 KiB
C

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017 NXP
*
* Peng Fan <peng.fan@nxp.com>
*/
#include <common.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/hab.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/syscounter.h>
#include <asm/armv8/mmu.h>
#include <dm/uclass.h>
#include <errno.h>
#include <fdt_support.h>
#include <fsl_wdog.h>
#include <imx_sip.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_IMX_HAB)
struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
.bank = 1,
.word = 3,
};
#endif
int timer_init(void)
{
#ifdef CONFIG_SPL_BUILD
struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
unsigned long freq = readl(&sctr->cntfid0);
/* Update with accurate clock frequency */
asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
#endif
gd->arch.tbl = 0;
gd->arch.tbu = 0;
return 0;
}
void enable_tzc380(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Enable TZASC and lock setting */
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
if (IS_ENABLED(CONFIG_IMX8MM))
setbits_le32(&gpr->gpr[10], BIT(1));
/*
* set Region 0 attribute to allow secure and non-secure
* read/write permission. Found some masters like usb dwc3
* controllers can't work with secure memory.
*/
writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
}
void set_wdog_reset(struct wdog_regs *wdog)
{
/*
* Output WDOG_B signal to reset external pmic or POR_B decided by
* the board design. Without external reset, the peripherals/DDR/
* PMIC are not reset, that may cause system working abnormal.
* WDZST bit is write-once only bit. Align this bit in kernel,
* otherwise kernel code will have no chance to set this bit.
*/
setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
}
static struct mm_region imx8m_mem_map[] = {
{
/* ROM */
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x100000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, {
/* CAAM */
.virt = 0x100000UL,
.phys = 0x100000UL,
.size = 0x8000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* TCM */
.virt = 0x7C0000UL,
.phys = 0x7C0000UL,
.size = 0x80000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* OCRAM */
.virt = 0x900000UL,
.phys = 0x900000UL,
.size = 0x200000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, {
/* AIPS */
.virt = 0xB00000UL,
.phys = 0xB00000UL,
.size = 0x3f500000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* DRAM1 */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = PHYS_SDRAM_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
#ifdef PHYS_SDRAM_2_SIZE
}, {
/* DRAM2 */
.virt = 0x100000000UL,
.phys = 0x100000000UL,
.size = PHYS_SDRAM_2_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
#endif
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = imx8m_mem_map;
void enable_caches(void)
{
/*
* If OPTEE runs, remove OPTEE memory from MMU table to
* avoid speculative prefetch. OPTEE runs at the top of
* the first memory bank
*/
if (rom_pointer[1])
imx8m_mem_map[5].size -= rom_pointer[1];
icache_enable();
dcache_enable();
}
static u32 get_cpu_variant_type(u32 type)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
struct fuse_bank *bank = &ocotp->bank[1];
struct fuse_bank1_regs *fuse =
(struct fuse_bank1_regs *)bank->fuse_regs;
u32 value = readl(&fuse->tester4);
if (type == MXC_CPU_IMX8MM) {
switch (value & 0x3) {
case 2:
if (value & 0x1c0000)
return MXC_CPU_IMX8MMDL;
else
return MXC_CPU_IMX8MMD;
case 3:
if (value & 0x1c0000)
return MXC_CPU_IMX8MMSL;
else
return MXC_CPU_IMX8MMS;
default:
if (value & 0x1c0000)
return MXC_CPU_IMX8MML;
break;
}
}
return type;
}
u32 get_cpu_rev(void)
{
struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
u32 reg = readl(&ana_pll->digprog);
u32 type = (reg >> 16) & 0xff;
u32 major_low = (reg >> 8) & 0xff;
u32 rom_version;
reg &= 0xff;
/* i.MX8MM */
if (major_low == 0x41) {
type = get_cpu_variant_type(MXC_CPU_IMX8MM);
} else {
if (reg == CHIP_REV_1_0) {
/*
* For B0 chip, the DIGPROG is not updated,
* it is still TO1.0. we have to check ROM
* version or OCOTP_READ_FUSE_DATA.
* 0xff0055aa is magic number for B1.
*/
if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
reg = CHIP_REV_2_1;
} else {
rom_version =
readl((void __iomem *)ROM_VERSION_A0);
if (rom_version != CHIP_REV_1_0) {
rom_version = readl((void __iomem *)ROM_VERSION_B0);
if (rom_version == CHIP_REV_2_0)
reg = CHIP_REV_2_0;
}
}
}
}
return (type << 12) | reg;
}
static void imx_set_wdog_powerdown(bool enable)
{
struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
/* Write to the PDE (Power Down Enable) bit */
writew(enable, &wdog1->wmcr);
writew(enable, &wdog2->wmcr);
writew(enable, &wdog3->wmcr);
}
int arch_cpu_init_dm(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
if (ret < 0) {
printf("Failed to find clock node. Check device tree\n");
return ret;
}
return 0;
}
int arch_cpu_init(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
/*
* ROM might disable clock for SCTR,
* enable the clock before timer_init.
*/
if (IS_ENABLED(CONFIG_SPL_BUILD))
clock_enable(CCGR_SCTR, 1);
/*
* Init timer at very early state, because sscg pll setting
* will use it
*/
timer_init();
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
clock_init();
imx_set_wdog_powerdown(false);
}
if (is_imx8mq()) {
clock_enable(CCGR_OCOTP, 1);
if (readl(&ocotp->ctrl) & 0x200)
writel(0x200, &ocotp->ctrl_clr);
}
return 0;
}
bool is_usb_boot(void)
{
return get_boot_device() == USB_BOOT;
}
#ifdef CONFIG_OF_SYSTEM_SETUP
int ft_system_setup(void *blob, bd_t *bd)
{
int i = 0;
int rc;
int nodeoff;
/* Disable the CPU idle for A0 chip since the HW does not support it */
if (is_soc_rev(CHIP_REV_1_0)) {
static const char * const nodes_path[] = {
"/cpus/cpu@0",
"/cpus/cpu@1",
"/cpus/cpu@2",
"/cpus/cpu@3",
};
for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
nodeoff = fdt_path_offset(blob, nodes_path[i]);
if (nodeoff < 0)
continue; /* Not found, skip it */
printf("Found %s node\n", nodes_path[i]);
rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
if (rc) {
printf("Unable to update property %s:%s, err=%s\n",
nodes_path[i], "status", fdt_strerror(rc));
return rc;
}
printf("Remove %s:%s\n", nodes_path[i],
"cpu-idle-states");
}
}
return 0;
}
#endif
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET)
void reset_cpu(ulong addr)
{
struct watchdog_regs *wdog = (struct watchdog_regs *)addr;
if (!addr)
wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
/* Clear WDA to trigger WDOG_B immediately */
writew((WCR_WDE | WCR_SRS), &wdog->wcr);
while (1) {
/*
* spin for .5 seconds before reset
*/
}
}
#endif