mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 18:41:03 +00:00
b1e1a42bb1
This patch sets the SICRL_LBC bits in SICRL to change the function of the associated pins to GPIO functionality. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
562 lines
17 KiB
C
562 lines
17 KiB
C
/*
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* Copyright (C) Sheldon Instruments, Inc. 2008
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* simpc8313 board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_NAND_U_BOOT
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#define CONFIG_E300 1
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#define CONFIG_MPC83xx 1
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#define CONFIG_MPC831x 1
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#define CONFIG_MPC8313 1
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#define CONFIG_PCI
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#define CONFIG_MISC_INIT_R
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/*
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* On-board devices
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*
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* TSEC1 is Marvell PHY 88E1118
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*/
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#define CONFIG_SYS_33MHZ
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#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
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#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
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#define CONFIG_SYS_IMMR 0xE0000000
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#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
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#endif
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#define CONFIG_SYS_MEMTEST_START 0x00001000
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#define CONFIG_SYS_MEMTEST_END 0x07f00000
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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/*
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* Device configurations
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*/
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#define CONFIG_TSEC1
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_MAX_MEM_MAPPED (512 << 20)
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#define CONFIG_SYS_DDRCDR ( DDRCDR_EN \
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| DDRCDR_PZ_NOMZ \
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| DDRCDR_NZ_NOMZ \
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| DDRCDR_M_ODR )
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/* 0x73000002 TODO ODR & DRN ? */
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
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#if !defined(CONFIG_NAND_SPL)
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#define CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
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#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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/*
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* Local Bus LCRR and LBCR regs
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*/
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
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#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
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| (0xFF << LBCR_BMT_SHIFT) \
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| 0xF ) /* 0x0004ff0f */
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#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
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/* drivers/mtd/nand/nand.c */
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_SYS_NAND_BASE 0xFFF00000
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#else
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#define CONFIG_SYS_NAND_BASE 0xE2800000
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#endif
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#define CONFIG_SYS_FPGA_BASE 0xFF000000
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_CMD_NAND 1
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
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#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
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#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
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#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
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#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8 bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V ) /* valid */
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#ifdef CONFIG_NAND_SP
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#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR )
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */
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#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
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#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
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#define NAND_CACHE_PAGES 32
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#elif defined(CONFIG_NAND_LP)
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#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \
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| OR_FCM_PGS \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR )
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */
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#define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
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#define NAND_CACHE_PAGES 64
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#else
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#error Page size of NAND not defined.
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#endif /* CONFIG_NAND_SP */
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#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
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#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
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#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
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#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_FPGA_BASE \
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| BR_PS_16 \
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| BR_MS_UPMA \
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| BR_V )
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#define CONFIG_SYS_OR1_PRELIM ( OR_AM_2MB \
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| OR_UPM_BCTLD)
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE
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#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_2MB)
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/*
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* JFFS2 configuration
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*/
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#define CONFIG_JFFS2_NAND
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#define CONFIG_JFFS2_DEV "nand0"
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/* mtdparts command line support */
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
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#define MTDIDS_DEFAULT "nand0=nand0"
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#define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_STDOUT_VIA_ALIAS 1
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_NS16550_MIN_FUNCTIONS
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#endif
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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/* I2C */
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#define CONFIG_FSL_I2C
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C2_OFFSET 0x3100
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
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#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
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#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
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#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
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/*
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* TSEC
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*/
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#define CONFIG_TSEC_ENET /* TSEC ethernet support */
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#define CONFIG_NET_MULTI
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#define CONFIG_GMII /* MII PHY management */
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#ifdef CONFIG_TSEC1
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#define CONFIG_HAS_ETH0
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define TSEC1_PHY_ADDR 0x0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC1_PHYIDX 0
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#endif
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#ifdef CONFIG_TSEC2
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#define CONFIG_HAS_ETH1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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#define TSEC2_PHY_ADDR 4
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#define TSEC2_FLAGS TSEC_GIGABIT
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#define TSEC2_PHYIDX 0
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#endif
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "TSEC1"
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/*
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* Configure on-board RTC
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*/
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#define CONFIG_RTC_DS1337
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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/*
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* Environment
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*/
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#if defined(CONFIG_NAND_U_BOOT)
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_ENV_OFFSET (768 * 1024)
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#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
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#elif !defined(CONFIG_SYS_RAMBOOT)
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
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#define CONFIG_ENV_SIZE 0x2000
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/* Address and size of Redundant Environment Sector */
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#else
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#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_FLASH
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_JFFS2
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#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
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#undef CONFIG_CMD_SAVEENV
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#undef CONFIG_CMD_LOADS
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#endif
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \
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+ sizeof(CONFIG_SYS_PROMPT) \
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+ 16 ) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
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#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
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#define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
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| 0x20000000 /* reserved */ \
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| HRCWL_DDR_TO_SCB_CLK_2X1 \
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| HRCWL_CSB_TO_CLKIN_4X1 \
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| HRCWL_CORE_TO_CSB_2_5X1 )
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#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
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#define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \
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| HRCWH_PCI1_ARBITER_ENABLE \
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| HRCWH_CORE_ENABLE \
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| HRCWH_BOOTSEQ_DISABLE \
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| HRCWH_SW_WATCHDOG_DISABLE \
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| HRCWH_TSEC1M_IN_RGMII \
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| HRCWH_TSEC2M_IN_RGMII \
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| HRCWH_BIG_ENDIAN \
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| HRCWH_LALE_NORMAL )
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#ifdef CONFIG_NAND_LP
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#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
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| HRCWH_FROM_0XFFF00100 \
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| HRCWH_ROM_LOC_NAND_LP_8BIT \
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| HRCWH_RL_EXT_NAND)
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#else
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#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
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| HRCWH_FROM_0XFFF00100 \
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| HRCWH_ROM_LOC_NAND_SP_8BIT \
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| HRCWH_RL_EXT_NAND )
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#endif
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/* System IO Config */
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#define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \
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| SICRH_ETSEC2_C \
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| SICRH_ETSEC2_D \
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| SICRH_ETSEC2_E \
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| SICRH_ETSEC2_F \
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| SICRH_ETSEC2_G \
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| SICRH_TSOBI1 \
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| SICRH_TSOBI2 )
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#define CONFIG_SYS_SICRL ( SICRL_LBC \
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| SICRL_USBDR \
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| SICRL_ETSEC2_A )
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#define CONFIG_SYS_HID0_INIT 0x000000000
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
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HID0_ENABLE_INSTRUCTION_CACHE | \
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HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
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#define CONFIG_SYS_HID2 HID2_HBE
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/* DDR @ 0x00000000 */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10)
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#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)
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/* PCI @ 0x80000000 */
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#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
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#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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/* PCI2 not supported on 8313 */
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#define CONFIG_SYS_IBAT4L (0)
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#define CONFIG_SYS_IBAT4U (0)
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/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
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/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
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#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT7L (0)
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#define CONFIG_SYS_IBAT7U (0)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
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#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
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#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
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#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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/*
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* Environment Configuration
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*/
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_NETDEV eth1
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#define CONFIG_HOSTNAME simpc8313
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#define CONFIG_ROOTPATH /tftpboot/
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#define CONFIG_BOOTFILE /tftpboot/uImage
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#define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */
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#define CONFIG_FDTFILE simpc8313.dtb
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#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
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#define CONFIG_BOOTDELAY 5 /* 5 second delay */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"
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#define XMK_STR(x) #x
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#define MK_STR(x) XMK_STR(x)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
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"ethprime=TSEC1\0" \
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"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
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"tftpflash=tftpboot $loadaddr $uboot; " \
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"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
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"erase " MK_STR(TEXT_BASE) " +$filesize; " \
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"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
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"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
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"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
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"fdtaddr=ae0000\0" \
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"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
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"console=ttyS0\0" \
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"setbootargs=setenv bootargs " \
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"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
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"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
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"load_uboot=tftp 100000 u-boot-nand.bin\0" \
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"burn_uboot=nand erase u-boot 80000; " \
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"nand write 100000 u-boot $filesize\0" \
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"update_uboot=run load_uboot;run burn_uboot\0" \
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"mtdids=nand0=nand0\0" \
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"mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
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"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
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"console=ttyS0,115200\0" \
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""
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv rootdev /dev/nfs;" \
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"run setbootargs;" \
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"run setipargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv rootdev /dev/ram;" \
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"run setbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#undef MK_STR
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#undef XMK_STR
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#endif /* __CONFIG_H */
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