mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 06:12:58 +00:00
46dc542870
Exposing set/way cache maintenance to a virtual machine is unsafe, not least because the instructions are not permission-checked but also because they are not broadcast between CPUs. Consequently, KVM traps and emulates such maintenance in the host kernel using by-VA operations and looping over the stage-2 page-tables. However, when running under protected KVM, these instructions are not able to be emulated and will instead result in an exception being delivered to the guest. Introduce CONFIG_CMO_BY_VA_ONLY so that virtual platforms can select this option and perform by-VA cache maintenance instead of using the set/way instructions. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Will Deacon <willdeacon@google.com> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com> [ Paul: pick from the Android tree. Fixup Pierre's commit. And fix some checkpatch warnings. Rebased to upstream. ] Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Tom Rini <trini@konsulko.com> Link:db5507f47fLink:2baf54e743
209 lines
7.2 KiB
Text
209 lines
7.2 KiB
Text
if ARM64
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config CMO_BY_VA_ONLY
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bool "Force cache maintenance to be exclusively by VA"
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depends on !SYS_DISABLE_DCACHE_OPS
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config ARMV8_SPL_EXCEPTION_VECTORS
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bool "Install crash dump exception vectors"
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depends on SPL
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help
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The default exception vector table is only used for the crash
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dump, but still takes quite a lot of space in the image size.
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Say N here if you are running out of code space in the image
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and want to save some space at the cost of less debugging info.
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config ARMV8_MULTIENTRY
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bool "Enable multiple CPUs to enter into U-Boot"
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config ARMV8_SET_SMPEN
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bool "Enable data coherency with other cores in cluster"
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help
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Say Y here if there is not any trust firmware to set
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CPUECTLR_EL1.SMPEN bit before U-Boot.
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For A53, it enables data coherency with other cores in the
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cluster, and for A57/A72, it enables receiving of instruction
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cache and TLB maintenance operations.
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Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
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for single core systems. Unfortunately write access to this
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register may be controlled by EL3/EL2 firmware. To be more
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precise, by default (if there is EL2/EL3 firmware running)
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this register is RO for NS EL1.
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This switch can be used to avoid writing to CPUECTLR_EL1,
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it can be safely enabled when EL2/EL3 initialized SMPEN bit
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or when CPU implementation doesn't include that register.
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config ARMV8_SWITCH_TO_EL1
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bool "Enable switching to running in EL1"
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help
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In some circumstances we need to switch to running in EL1.
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Enable this option to have U-Boot switch to EL1.
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config ARMV8_SPIN_TABLE
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bool "Support spin-table enable method"
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depends on ARMV8_MULTIENTRY && OF_LIBFDT
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help
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Say Y here to support "spin-table" enable method for booting Linux.
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To use this feature, you must do:
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- Specify enable-method = "spin-table" in each CPU node in the
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Device Tree you are using to boot the kernel
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- Bring secondary CPUs into U-Boot proper in a board specific
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manner. This must be done *after* relocation. Otherwise, the
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secondary CPUs will spin in unprotected memory area because the
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master CPU protects the relocated spin code.
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U-Boot automatically does:
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- Set "cpu-release-addr" property of each CPU node
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(overwrites it if already exists).
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- Reserve the code for the spin-table and the release address
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via a /memreserve/ region in the Device Tree.
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menu "ARMv8 secure monitor firmware"
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config ARMV8_SEC_FIRMWARE_SUPPORT
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bool "Enable ARMv8 secure monitor firmware framework support"
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select FIT
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select OF_LIBFDT
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help
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This framework is aimed at making secure monitor firmware load
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process brief.
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Note: Only FIT format image is supported.
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You should prepare and provide the below information:
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- Address of secure firmware.
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- Address to hold the return address from secure firmware.
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- Secure firmware FIT image related information.
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Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMWARE_FIT_CNF_NAME
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- The target exception level that secure monitor firmware will
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return to.
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config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
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bool "Enable ARMv8 secure monitor firmware framework support for SPL"
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depends on SPL
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select SPL_FIT
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select SPL_OF_LIBFDT
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help
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Say Y here to support this framework in SPL phase.
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config SPL_RECOVER_DATA_SECTION
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bool "save/restore SPL data section"
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depends on SPL
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help
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Say Y here to save SPL data section for cold boot, and restore
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at warm boot in SPL phase.
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config SEC_FIRMWARE_ARMV8_PSCI
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bool "PSCI implementation in secure monitor firmware"
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depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
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depends on ARMV8_PSCI=n
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help
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This config enables the ARMv8 PSCI implementation in secure monitor
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firmware. This is a private PSCI implementation and different from
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those implemented under the common ARMv8 PSCI framework.
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config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
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bool "ARMv8 secure monitor firmware ERET address byteorder swap"
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depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
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help
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Say Y here when the endianness of the register or memory holding the
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Secure firmware exception return address is different with core's.
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endmenu
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config PSCI_RESET
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bool "Use PSCI for reset and shutdown"
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default y
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select ARM_SMCCC if OF_CONTROL
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depends on !ARCH_APPLE && !ARCH_BCM283X && !ARCH_EXYNOS7 && \
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!TARGET_LS2080AQDS && \
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!TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
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!TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
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!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
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!TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
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!TARGET_LS1012AFRWY && \
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!TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \
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!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
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!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
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!TARGET_LS1046AFRWY && \
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!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
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!TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
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!ARCH_UNIPHIER
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help
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Most armv8 systems have PSCI support enabled in EL3, either through
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ARM Trusted Firmware or other firmware.
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On these systems, we do not need to implement system reset manually,
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but can instead rely on higher level firmware to deal with it.
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Select Y here to make use of PSCI calls for system reset
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config SYS_HAS_ARMV8_SECURE_BASE
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bool
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config ARMV8_PSCI
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bool "Enable PSCI support" if EXPERT
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help
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PSCI is Power State Coordination Interface defined by ARM.
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The PSCI in U-boot provides a general framework and each platform
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can implement their own specific PSCI functions.
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Say Y here to enable PSCI support on ARMv8 platform.
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config ARMV8_PSCI_NR_CPUS
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int "Maximum supported CPUs for PSCI"
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depends on ARMV8_PSCI
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default 4
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help
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The maximum number of CPUs supported in the PSCI firmware.
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It is no problem to set a larger value than the number of CPUs in
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the actual hardware implementation.
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config ARMV8_PSCI_CPUS_PER_CLUSTER
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int "Number of CPUs per cluster"
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depends on ARMV8_PSCI
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default 0
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help
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The number of CPUs per cluster, suppose each cluster has same number
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of CPU cores, platforms with asymmetric clusters don't apply here.
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A value 0 or no definition of it works for single cluster system.
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System with multi-cluster should difine their own exact value.
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config ARMV8_PSCI_RELOCATE
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bool "Relocate PSCI code"
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depends on ARMV8_PSCI
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depends on SYS_HAS_ARMV8_SECURE_BASE
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help
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Relocate PSCI code, for example to a secure memory on the SoC. If not
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set, the PSCI sections are placed together with the u-boot and the
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regions will be marked as reserved before linux is started.
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config ARMV8_SECURE_BASE
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hex "Secure address for PSCI image"
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depends on ARMV8_PSCI_RELOCATE
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default 0x18000000 if ARCH_LS1028A
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help
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Address for placing the PSCI text, data and stack sections.
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config ARMV8_EA_EL3_FIRST
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bool "External aborts and SError interrupt exception are taken in EL3"
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help
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Exception handling at all exception levels for External Abort and
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SError interrupt exception are taken in EL3.
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menuconfig ARMV8_CRYPTO
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bool "ARM64 Accelerated Cryptographic Algorithms"
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if ARMV8_CRYPTO
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config ARMV8_CE_SHA1
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bool "SHA-1 digest algorithm (ARMv8 Crypto Extensions)"
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default y if SHA1
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config ARMV8_CE_SHA256
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bool "SHA-256 digest algorithm (ARMv8 Crypto Extensions)"
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default y if SHA256
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endif
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endif
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