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ef76ebb1ef
The maximum device and arm speeds can be determined by reading EFUSE_BOOTROM register. As there is already a framework for reading this register, adding support for all possible speeds on k2g devices. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
136 lines
2.5 KiB
C
136 lines
2.5 KiB
C
/*
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* keystone2: common clock header file
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_CLOCK_H
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#define __ASM_ARCH_CLOCK_H
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_SOC_K2HK
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#include <asm/arch/clock-k2hk.h>
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#endif
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#ifdef CONFIG_SOC_K2E
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#include <asm/arch/clock-k2e.h>
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#endif
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#ifdef CONFIG_SOC_K2L
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#include <asm/arch/clock-k2l.h>
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#endif
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#ifdef CONFIG_SOC_K2G
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#include <asm/arch/clock-k2g.h>
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#endif
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#define CORE_PLL MAIN_PLL
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#define DDR3_PLL DDR3A_PLL
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#define NSS_PLL PASS_PLL
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#define CLK_LIST(CLK)\
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CLK(0, core_pll_clk)\
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CLK(1, pass_pll_clk)\
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CLK(2, tetris_pll_clk)\
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CLK(3, ddr3a_pll_clk)\
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CLK(4, ddr3b_pll_clk)\
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CLK(5, sys_clk0_clk)\
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CLK(6, sys_clk0_1_clk)\
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CLK(7, sys_clk0_2_clk)\
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CLK(8, sys_clk0_3_clk)\
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CLK(9, sys_clk0_4_clk)\
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CLK(10, sys_clk0_6_clk)\
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CLK(11, sys_clk0_8_clk)\
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CLK(12, sys_clk0_12_clk)\
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CLK(13, sys_clk0_24_clk)\
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CLK(14, sys_clk1_clk)\
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CLK(15, sys_clk1_3_clk)\
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CLK(16, sys_clk1_4_clk)\
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CLK(17, sys_clk1_6_clk)\
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CLK(18, sys_clk1_12_clk)\
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CLK(19, sys_clk2_clk)\
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CLK(20, sys_clk3_clk)\
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CLK(21, uart_pll_clk)
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#include <asm/types.h>
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#define GENERATE_ENUM(NUM, ENUM) ENUM = NUM,
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#define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n"
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#define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR)
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enum {
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SPD200,
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SPD400,
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SPD600,
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SPD800,
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SPD850,
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SPD900,
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SPD1000,
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SPD1200,
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SPD1250,
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SPD1350,
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SPD1400,
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SPD1500,
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NUM_SPDS,
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};
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/* PLL identifiers */
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enum {
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MAIN_PLL,
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TETRIS_PLL,
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PASS_PLL,
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DDR3A_PLL,
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DDR3B_PLL,
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UART_PLL,
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MAX_PLL_COUNT,
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};
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enum ext_clk_e {
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sys_clk,
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alt_core_clk,
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pa_clk,
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tetris_clk,
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ddr3a_clk,
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ddr3b_clk,
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uart_clk,
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ext_clk_count /* number of external clocks */
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};
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enum clk_e {
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CLK_LIST(GENERATE_ENUM)
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};
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struct keystone_pll_regs {
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u32 reg0;
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u32 reg1;
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};
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/* PLL configuration data */
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struct pll_init_data {
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int pll;
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int pll_m; /* PLL Multiplier */
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int pll_d; /* PLL divider */
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int pll_od; /* PLL output divider */
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};
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extern unsigned int external_clk[ext_clk_count];
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extern const struct keystone_pll_regs keystone_pll_regs[];
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extern s16 divn_val[];
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extern int speeds[];
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void init_plls(void);
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void init_pll(const struct pll_init_data *data);
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struct pll_init_data *get_pll_init_data(int pll);
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unsigned long clk_get_rate(unsigned int clk);
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unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
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int clk_set_rate(unsigned int clk, unsigned long hz);
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int get_max_dev_speed(int *spds);
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int get_max_arm_speed(int *spds);
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void pll_pa_clk_sel(void);
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#endif
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#endif
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