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e1be0d25ec
This errata fix is required for 32 bit DDR2 controller on 8572. May also be required for P10XX20XX platforms Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
173 lines
5.3 KiB
C
173 lines
5.3 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#ifndef FSL_DDR_MEMCTL_H
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#define FSL_DDR_MEMCTL_H
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/*
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* Pick a basic DDR Technology.
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*/
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#include <ddr_spd.h>
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#define SDRAM_TYPE_DDR1 2
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#define SDRAM_TYPE_DDR2 3
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#define SDRAM_TYPE_LPDDR1 6
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#define SDRAM_TYPE_DDR3 7
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#if defined(CONFIG_FSL_DDR1)
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#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
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typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
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#ifndef CONFIG_FSL_SDRAM_TYPE
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#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
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#endif
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#elif defined(CONFIG_FSL_DDR2)
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#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
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typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
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#ifndef CONFIG_FSL_SDRAM_TYPE
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#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
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#endif
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#elif defined(CONFIG_FSL_DDR3)
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#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
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typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
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#ifndef CONFIG_FSL_SDRAM_TYPE
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#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
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#endif
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#endif /* #if defined(CONFIG_FSL_DDR1) */
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/* define bank(chip select) interleaving mode */
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#define FSL_DDR_CS0_CS1 0x40
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#define FSL_DDR_CS2_CS3 0x20
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#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
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#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
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/* define memory controller interleaving mode */
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#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
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#define FSL_DDR_PAGE_INTERLEAVING 0x1
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#define FSL_DDR_BANK_INTERLEAVING 0x2
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#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
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/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
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*/
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#define SDRAM_CFG_MEM_EN 0x80000000
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#define SDRAM_CFG_SREN 0x40000000
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#define SDRAM_CFG_ECC_EN 0x20000000
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#define SDRAM_CFG_RD_EN 0x10000000
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#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
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#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
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#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
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#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
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#define SDRAM_CFG_DYN_PWR 0x00200000
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#define SDRAM_CFG_32_BE 0x00080000
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#define SDRAM_CFG_8_BE 0x00040000
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#define SDRAM_CFG_NCAP 0x00020000
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#define SDRAM_CFG_2T_EN 0x00008000
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#define SDRAM_CFG_BI 0x00000001
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/* Record of register values computed */
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typedef struct fsl_ddr_cfg_regs_s {
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struct {
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unsigned int bnds;
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unsigned int config;
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unsigned int config_2;
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} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
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unsigned int timing_cfg_3;
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unsigned int timing_cfg_0;
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unsigned int timing_cfg_1;
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unsigned int timing_cfg_2;
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unsigned int ddr_sdram_cfg;
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unsigned int ddr_sdram_cfg_2;
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unsigned int ddr_sdram_mode;
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unsigned int ddr_sdram_mode_2;
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unsigned int ddr_sdram_md_cntl;
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unsigned int ddr_sdram_interval;
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unsigned int ddr_data_init;
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unsigned int ddr_sdram_clk_cntl;
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unsigned int ddr_init_addr;
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unsigned int ddr_init_ext_addr;
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unsigned int timing_cfg_4;
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unsigned int timing_cfg_5;
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unsigned int ddr_zq_cntl;
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unsigned int ddr_wrlvl_cntl;
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unsigned int ddr_pd_cntl;
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unsigned int ddr_sr_cntr;
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unsigned int ddr_sdram_rcw_1;
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unsigned int ddr_sdram_rcw_2;
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} fsl_ddr_cfg_regs_t;
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typedef struct memctl_options_partial_s {
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unsigned int all_DIMMs_ECC_capable;
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unsigned int all_DIMMs_tCKmax_ps;
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unsigned int all_DIMMs_burst_lengths_bitmask;
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unsigned int all_DIMMs_registered;
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unsigned int all_DIMMs_unbuffered;
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/* unsigned int lowest_common_SPD_caslat; */
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unsigned int all_DIMMs_minimum_tRCD_ps;
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} memctl_options_partial_t;
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/*
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* Generalized parameters for memory controller configuration,
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* might be a little specific to the FSL memory controller
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*/
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typedef struct memctl_options_s {
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/*
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* Memory organization parameters
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*
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* if DIMM is present in the system
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* where DIMMs are with respect to chip select
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* where chip selects are with respect to memory boundaries
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*/
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unsigned int registered_dimm_en; /* use registered DIMM support */
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/* Options local to a Chip Select */
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struct cs_local_opts_s {
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unsigned int auto_precharge;
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unsigned int odt_rd_cfg;
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unsigned int odt_wr_cfg;
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} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
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/* Special configurations for chip select */
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unsigned int memctl_interleaving;
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unsigned int memctl_interleaving_mode;
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unsigned int ba_intlv_ctl;
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/* Operational mode parameters */
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unsigned int ECC_mode; /* Use ECC? */
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/* Initialize ECC using memory controller? */
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unsigned int ECC_init_using_memctl;
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unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */
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/* SREN - self-refresh during sleep */
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unsigned int self_refresh_in_sleep;
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unsigned int dynamic_power; /* DYN_PWR */
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/* memory data width to use (16-bit, 32-bit, 64-bit) */
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unsigned int data_bus_width;
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unsigned int burst_length; /* 4, 8 */
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/* Global Timing Parameters */
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unsigned int cas_latency_override;
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unsigned int cas_latency_override_value;
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unsigned int use_derated_caslat;
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unsigned int additive_latency_override;
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unsigned int additive_latency_override_value;
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unsigned int clk_adjust; /* */
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unsigned int cpo_override;
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unsigned int write_data_delay; /* DQS adjust */
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unsigned int half_strength_driver_enable;
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unsigned int twoT_en;
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unsigned int threeT_en;
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unsigned int bstopre;
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unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
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unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
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/* Automatic self refresh */
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unsigned int auto_self_refresh_en;
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unsigned int sr_it;
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} memctl_options_t;
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extern phys_size_t fsl_ddr_sdram(void);
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#endif
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