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The i.MX6Q/DL sabreauto board has one NAND socket, set the CONFIG_NAND_MXS and relevant NAND configurations to enable the MXS NAND flash driver. Add board level codes to set IOMUX and clock for GPMI-NAND and BCH module. Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
67 lines
1.8 KiB
C
67 lines
1.8 KiB
C
/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the Freescale i.MX6Q SabreAuto board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MX6QSABREAUTO_CONFIG_H
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#define __MX6QSABREAUTO_CONFIG_H
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#define CONFIG_MACH_TYPE 3529
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#define CONFIG_MXC_UART_BASE UART4_BASE
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#define CONFIG_CONSOLE_DEV "ttymxc3"
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#if defined CONFIG_MX6Q
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#define CONFIG_DEFAULT_FDT_FILE "imx6q-sabreauto.dtb"
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#elif defined CONFIG_MX6DL
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#define CONFIG_DEFAULT_FDT_FILE "imx6dl-sabreauto.dtb"
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#endif
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#define CONFIG_MMCROOT "/dev/mmcblk0p2"
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#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
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/* USB Configs */
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#define CONFIG_CMD_USB
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_MX6
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#define CONFIG_USB_STORAGE
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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#define CONFIG_PCA953X
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#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
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#include "mx6sabre_common.h"
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#if defined(CONFIG_ENV_IS_IN_MMC)
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#endif
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/* I2C Configs */
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#define CONFIG_CMD_I2C
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_SPEED 100000
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/* NAND flash command */
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NAND_TRIMFFS
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/* NAND stuff */
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#define CONFIG_NAND_MXS
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* DMA stuff, needed for GPMI/MXS NAND support */
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#define CONFIG_APBH_DMA
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#define CONFIG_APBH_DMA_BURST
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#define CONFIG_APBH_DMA_BURST8
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#endif /* __MX6QSABREAUTO_CONFIG_H */
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