mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 08:31:03 +00:00
b60774fff1
K2G SoC has a Cadence QSPI controller to communicate with NOR flash devices. Add DT nodes to support the same. Also, K2G EVM has a s25fl512s flash connect to QSPI bus at CS 0. Add nor flash slave node for the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
153 lines
3.4 KiB
Text
153 lines
3.4 KiB
Text
/*
|
|
* Copyright 2014 Texas Instruments, Inc.
|
|
*
|
|
* Keystone 2 Galileo soc device tree
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include "skeleton.dtsi"
|
|
|
|
/ {
|
|
model = "Texas Instruments Keystone 2 SoC";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupt-parent = <&gic>;
|
|
|
|
aliases {
|
|
serial0 = &uart0;
|
|
spi0 = &spi0;
|
|
spi1 = &spi1;
|
|
spi2 = &spi2;
|
|
spi3 = &spi3;
|
|
spi4 = &qspi;
|
|
};
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x80000000 0x80000000>;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
interrupt-parent = <&gic>;
|
|
|
|
cpu@0 {
|
|
compatible = "arm,cortex-a15";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
gic: interrupt-controller {
|
|
compatible = "arm,cortex-a15-gic";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
reg = <0x0 0x02561000 0x0 0x1000>,
|
|
<0x0 0x02562000 0x0 0x2000>,
|
|
<0x0 0x02564000 0x0 0x1000>,
|
|
<0x0 0x02566000 0x0 0x2000>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
|
|
IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "ti,keystone","simple-bus";
|
|
interrupt-parent = <&gic>;
|
|
ranges;
|
|
|
|
uart0: serial@02530c00 {
|
|
compatible = "ns16550a";
|
|
current-speed = <115200>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
reg = <0x02530c00 0x100>;
|
|
clock-names = "uart";
|
|
interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
|
|
mdio: mdio@4200f00 {
|
|
compatible = "ti,keystone_mdio", "ti,davinci_mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
/* power-domains = <&k2g_pds K2G_DEV_NSS0>; */
|
|
/* clocks = <&k2g_clks K2G_DEV_NSS0 K2G_DEV_NSS_ESW_CLK>; */
|
|
clock-names = "fck";
|
|
reg = <0x04200f00 0x100>;
|
|
status = "disabled";
|
|
bus_freq = <2500000>;
|
|
};
|
|
|
|
qspi: qspi@2940000 {
|
|
compatible = "cadence,qspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x02940000 0x1000>,
|
|
<0x24000000 0x4000000>;
|
|
interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
|
|
num-cs = <4>;
|
|
fifo-depth = <256>;
|
|
sram-size = <256>;
|
|
status = "disabled";
|
|
};
|
|
|
|
#include "k2g-netcp.dtsi"
|
|
|
|
pmmc: pmmc@2900000 {
|
|
compatible = "ti,power-processor";
|
|
reg = <0x02900000 0x40000>;
|
|
ti,lpsc_module = <1>;
|
|
};
|
|
|
|
spi0: spi@21805400 {
|
|
compatible = "ti,keystone-spi", "ti,dm6441-spi";
|
|
reg = <0x21805400 0x200>;
|
|
num-cs = <4>;
|
|
ti,davinci-spi-intr-line = <0>;
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@21805800 {
|
|
compatible = "ti,keystone-spi", "ti,dm6441-spi";
|
|
reg = <0x21805800 0x200>;
|
|
num-cs = <4>;
|
|
ti,davinci-spi-intr-line = <0>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@21805c00 {
|
|
compatible = "ti,keystone-spi", "ti,dm6441-spi";
|
|
reg = <0x21805C00 0x200>;
|
|
num-cs = <4>;
|
|
ti,davinci-spi-intr-line = <0>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@21806000 {
|
|
compatible = "ti,keystone-spi", "ti,dm6441-spi";
|
|
reg = <0x21806000 0x200>;
|
|
num-cs = <4>;
|
|
ti,davinci-spi-intr-line = <0>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|