mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 11:18:28 +00:00
396 lines
11 KiB
C
396 lines
11 KiB
C
/*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx51_pins.h>
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#include <asm/arch/iomux.h>
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#include <asm/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include "mx51evk.h"
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DECLARE_GLOBAL_DATA_PTR;
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static u32 system_rev;
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struct io_board_ctrl *mx51_io_board;
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR, 1, 1},
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{MMC_SDHC2_BASE_ADDR, 1, 1},
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};
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#endif
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u32 get_board_rev(void)
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{
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return system_rev;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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static void setup_iomux_uart(void)
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{
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unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
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PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
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mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
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mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
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mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
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mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
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}
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static void setup_expio(void)
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{
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u32 reg;
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struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
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struct clkctl *pclkctl = (struct clkctl *)CCM_BASE_ADDR;
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/* CS5 setup */
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mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
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writel(0x00410089, &pweim[5].csgcr1);
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writel(0x00000002, &pweim[5].csgcr2);
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/* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
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writel(0x32260000, &pweim[5].csrcr1);
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/* APR = 0 */
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writel(0x00000000, &pweim[5].csrcr2);
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/*
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* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
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* WCSA=0, WCSN=0
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*/
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writel(0x72080F00, &pweim[5].cswcr1);
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mx51_io_board = (struct io_board_ctrl *)(CS5_BASE_ADDR +
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IO_BOARD_OFFSET);
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if ((readw(&mx51_io_board->id1) == 0xAAAA) &&
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(readw(&mx51_io_board->id2) == 0x5555)) {
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if (is_soc_rev(CHIP_REV_2_0) < 0) {
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reg = readl(&pclkctl->cbcdr);
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reg = (reg & (~0x70000)) | 0x30000;
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writel(reg, &pclkctl->cbcdr);
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/* make sure divider effective */
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while (readl(&pclkctl->cdhipr) != 0)
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;
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writel(0x0, &pclkctl->ccdr);
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}
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} else {
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/* CS1 */
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writel(0x00410089, &pweim[1].csgcr1);
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writel(0x00000002, &pweim[1].csgcr2);
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/* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
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writel(0x32260000, &pweim[1].csrcr1);
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/* APR=0 */
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writel(0x00000000, &pweim[1].csrcr2);
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/*
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* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
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* WEN=0, WCSA=0, WCSN=0
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*/
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writel(0x72080F00, &pweim[1].cswcr1);
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mx51_io_board = (struct io_board_ctrl *)(CS1_BASE_ADDR +
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IO_BOARD_OFFSET);
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}
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/* Reset interrupt status reg */
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writew(0x1F, &(mx51_io_board->int_rest));
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writew(0x00, &(mx51_io_board->int_rest));
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writew(0xFFFF, &(mx51_io_board->int_mask));
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/* Reset the XUART and Ethernet controllers */
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reg = readw(&(mx51_io_board->sw_reset));
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reg |= 0x9;
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writew(reg, &(mx51_io_board->sw_reset));
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reg &= ~0x9;
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writew(reg, &(mx51_io_board->sw_reset));
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}
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static void setup_iomux_fec(void)
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{
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/*FEC_MDIO*/
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mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
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/*FEC_MDC*/
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mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
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/* FEC RDATA[3] */
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mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
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/* FEC RDATA[2] */
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mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
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/* FEC RDATA[1] */
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mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
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/* FEC RDATA[0] */
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mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
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/* FEC TDATA[3] */
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mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
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/* FEC TDATA[2] */
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mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
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/* FEC TDATA[1] */
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mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
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/* FEC TDATA[0] */
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mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
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/* FEC TX_EN */
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mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
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/* FEC TX_ER */
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mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
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/* FEC TX_CLK */
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mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
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/* FEC TX_COL */
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mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
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/* FEC RX_CLK */
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mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
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/* FEC RX_CRS */
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mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
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/* FEC RX_ER */
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mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
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/* FEC RX_DV */
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mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
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}
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#ifdef CONFIG_FSL_ESDHC
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int board_mmc_getcd(u8 *cd, struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
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*cd = readl(GPIO1_BASE_ADDR) & 0x01;
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else
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*cd = readl(GPIO1_BASE_ADDR) & 0x40;
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return 0;
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}
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int board_mmc_init(bd_t *bis)
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{
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u32 index;
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s32 status = 0;
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
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index++) {
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switch (index) {
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case 0:
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mxc_request_iomux(MX51_PIN_SD1_CMD,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_CLK,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_DATA0,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_DATA1,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_DATA2,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD1_DATA3,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
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PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
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PAD_CTL_PUE_PULL |
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PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
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mxc_request_iomux(MX51_PIN_GPIO1_0,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
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PAD_CTL_HYS_ENABLE);
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mxc_request_iomux(MX51_PIN_GPIO1_1,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
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PAD_CTL_HYS_ENABLE);
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break;
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case 1:
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mxc_request_iomux(MX51_PIN_SD2_CMD,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD2_CLK,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_SD2_DATA0,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX51_PIN_SD2_DATA1,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX51_PIN_SD2_DATA2,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX51_PIN_SD2_DATA3,
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IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
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PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
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PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
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PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
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PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
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PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
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PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
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PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
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PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
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PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
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PAD_CTL_SRE_FAST);
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mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
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PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
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PAD_CTL_SRE_FAST);
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mxc_request_iomux(MX51_PIN_SD2_CMD,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX51_PIN_GPIO1_6,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
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PAD_CTL_HYS_ENABLE);
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mxc_request_iomux(MX51_PIN_GPIO1_5,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
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PAD_CTL_HYS_ENABLE);
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break;
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default:
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printf("Warning: you configured more ESDHC controller"
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"(%d) as supported by the board(2)\n",
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CONFIG_SYS_FSL_ESDHC_NUM);
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return status;
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}
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status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
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}
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return status;
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}
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#endif
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int board_init(void)
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{
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system_rev = get_cpu_rev();
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gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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setup_iomux_uart();
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setup_expio();
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setup_iomux_fec();
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: MX51EVK ");
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switch (system_rev & 0xff) {
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case CHIP_REV_3_0:
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puts("3.0 [");
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break;
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case CHIP_REV_2_5:
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puts("2.5 [");
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break;
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case CHIP_REV_2_0:
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puts("2.0 [");
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break;
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case CHIP_REV_1_1:
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puts("1.1 [");
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break;
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case CHIP_REV_1_0:
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default:
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puts("1.0 [");
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break;
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}
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switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
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case 0x0001:
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puts("POR");
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break;
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case 0x0009:
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puts("RST");
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break;
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case 0x0010:
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case 0x0011:
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puts("WDOG");
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break;
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default:
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puts("unknown");
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}
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puts("]\n");
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return 0;
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}
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