mirror of
https://github.com/AsahiLinux/u-boot
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a280e9db64
Add mailbox support for Stratix SoC Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Reviewed-by: Marek Vasut <marex@denx.de>
144 lines
4.9 KiB
C
144 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
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*
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*/
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#ifndef _MAILBOX_S10_H_
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#define _MAILBOX_S10_H_
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/* user define Uboot ID */
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#define MBOX_CLIENT_ID_UBOOT 0xB
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#define MBOX_ID_UBOOT 0x1
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#define MBOX_CMD_DIRECT 0
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#define MBOX_CMD_INDIRECT 1
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#define MBOX_MAX_CMD_INDEX 2047
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#define MBOX_CMD_BUFFER_SIZE 32
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#define MBOX_RESP_BUFFER_SIZE 16
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#define MBOX_HDR_CMD_LSB 0
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#define MBOX_HDR_CMD_MSK (BIT(11) - 1)
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#define MBOX_HDR_I_LSB 11
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#define MBOX_HDR_I_MSK BIT(11)
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#define MBOX_HDR_LEN_LSB 12
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#define MBOX_HDR_LEN_MSK 0x007FF000
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#define MBOX_HDR_ID_LSB 24
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#define MBOX_HDR_ID_MSK 0x0F000000
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#define MBOX_HDR_CLIENT_LSB 28
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#define MBOX_HDR_CLIENT_MSK 0xF0000000
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/* Interrupt flags */
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#define MBOX_FLAGS_INT_COE BIT(0) /* COUT update interrupt enable */
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#define MBOX_FLAGS_INT_RIE BIT(1) /* RIN update interrupt enable */
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#define MBOX_FLAGS_INT_UAE BIT(8) /* Urgent ACK interrupt enable */
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#define MBOX_ALL_INTRS (MBOX_FLAGS_INT_COE | \
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MBOX_FLAGS_INT_RIE | \
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MBOX_FLAGS_INT_UAE)
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/* Status */
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#define MBOX_STATUS_UA_MSK BIT(8)
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#define MBOX_CMD_HEADER(client, id, len, indirect, cmd) \
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((((cmd) << MBOX_HDR_CMD_LSB) & MBOX_HDR_CMD_MSK) | \
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(((indirect) << MBOX_HDR_I_LSB) & MBOX_HDR_I_MSK) | \
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(((len) << MBOX_HDR_LEN_LSB) & MBOX_HDR_LEN_MSK) | \
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(((id) << MBOX_HDR_ID_LSB) & MBOX_HDR_ID_MSK) | \
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(((client) << MBOX_HDR_CLIENT_LSB) & MBOX_HDR_CLIENT_MSK))
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#define MBOX_RESP_ERR_GET(resp) \
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(((resp) & MBOX_HDR_CMD_MSK) >> MBOX_HDR_CMD_LSB)
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#define MBOX_RESP_LEN_GET(resp) \
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(((resp) & MBOX_HDR_LEN_MSK) >> MBOX_HDR_LEN_LSB)
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#define MBOX_RESP_ID_GET(resp) \
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(((resp) & MBOX_HDR_ID_MSK) >> MBOX_HDR_ID_LSB)
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#define MBOX_RESP_CLIENT_GET(resp) \
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(((resp) & MBOX_HDR_CLIENT_MSK) >> MBOX_HDR_CLIENT_LSB)
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/* Response error list */
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enum ALT_SDM_MBOX_RESP_CODE {
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/* CMD completed successfully, but check resp ARGS for any errors */
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MBOX_RESP_STATOK = 0,
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/* CMD is incorrectly formatted in some way */
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MBOX_RESP_INVALID_COMMAND = 1,
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/* BootROM Command code not undesrtood */
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MBOX_RESP_UNKNOWN_BR = 2,
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/* CMD code not recognized by firmware */
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MBOX_RESP_UNKNOWN = 3,
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/* Indicates that the device is not configured */
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MBOX_RESP_NOT_CONFIGURED = 256,
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/* Indicates that the device is busy */
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MBOX_RESP_DEVICE_BUSY = 0x1FF,
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/* Indicates that there is no valid response available */
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MBOX_RESP_NO_VALID_RESP_AVAILABLE = 0x2FF,
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/* General Error */
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MBOX_RESP_ERROR = 0x3FF,
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};
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/* Mailbox command list */
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#define MBOX_RESTART 2
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#define MBOX_CONFIG_STATUS 4
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#define MBOX_RECONFIG 6
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#define MBOX_RECONFIG_MSEL 7
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#define MBOX_RECONFIG_DATA 8
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#define MBOX_RECONFIG_STATUS 9
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#define MBOX_QSPI_OPEN 50
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#define MBOX_QSPI_CLOSE 51
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#define MBOX_QSPI_DIRECT 59
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#define MBOX_REBOOT_HPS 71
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/* Mailbox registers */
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#define MBOX_CIN 0 /* command valid offset */
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#define MBOX_ROUT 4 /* response output offset */
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#define MBOX_URG 8 /* urgent command */
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#define MBOX_FLAGS 0x0c /* interrupt enables */
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#define MBOX_COUT 0x20 /* command free offset */
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#define MBOX_RIN 0x24 /* respond valid offset */
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#define MBOX_STATUS 0x2c /* mailbox status */
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#define MBOX_CMD_BUF 0x40 /* circular command buffer */
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#define MBOX_RESP_BUF 0xc0 /* circular response buffer */
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#define MBOX_DOORBELL_TO_SDM 0x400 /* Doorbell to SDM */
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#define MBOX_DOORBELL_FROM_SDM 0x480 /* Doorbell from SDM */
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/* Status and bit information returned by RECONFIG_STATUS */
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#define RECONFIG_STATUS_RESPONSE_LEN 6
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#define RECONFIG_STATUS_STATE 0
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#define RECONFIG_STATUS_PIN_STATUS 2
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#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
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#define MBOX_CFGSTAT_STATE_IDLE 0x00000000
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#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000
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#define MBOX_CFGSTAT_STATE_FAILACK 0x08000000
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#define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001
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#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002
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#define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003
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#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004
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#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005
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#define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006
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#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007
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#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008
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#define RCF_SOFTFUNC_STATUS_CONF_DONE BIT(0)
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#define RCF_SOFTFUNC_STATUS_INIT_DONE BIT(1)
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#define RCF_SOFTFUNC_STATUS_SEU_ERROR BIT(3)
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#define RCF_PIN_STATUS_NSTATUS BIT(31)
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int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg, u8 urgent,
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u32 *resp_buf_len, u32 *resp_buf);
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int mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
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u8 urgent, u32 *resp_buf_len, u32 *resp_buf);
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int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
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int mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg);
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int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len);
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int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len);
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int mbox_init(void);
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#ifdef CONFIG_CADENCE_QSPI
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int mbox_qspi_close(void);
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int mbox_qspi_open(void);
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#endif
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int mbox_reset_cold(void);
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#endif /* _MAILBOX_S10_H_ */
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