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126fe70d77
LS1046AQDS Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
44 lines
1,012 B
C
44 lines
1,012 B
C
/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DDR_H__
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#define __DDR_H__
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void erratum_a008850_post(void);
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 rank_gb;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 wrlvl_ctl_2;
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u32 wrlvl_ctl_3;
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};
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/*
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* These tables contain all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
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*/
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{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
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{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
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{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
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{2, 2300, 0, 8, 9, 0x0A0C0D11, 0x1214150E,},
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{}
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};
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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};
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#endif
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