mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 10:18:38 +00:00
7a3620b246
Some UniPhier boards are equipped with an expansion slot that
some optional SRAM/NOR-flash cards can be attached to. So, run-time
detection of the number of flash banks would be more user-friendly.
Until this commit, UniPhier boards have achieved this by (ab)using
board_flash_wp_on() because the boot failed if flash_size got zero.
Fortunately, this problem was solved by commit 70879a9256 (flash:
do not fail even if flash_size is zero).
Now it is possible to throw away such a tricky workaround. This
commit also enables CONFIG_SYS_MAX_FLASH_BANKS_DETECT for further
refactoring.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
288 lines
8 KiB
C
288 lines
8 KiB
C
/*
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* Copyright (C) 2012-2014 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* U-boot - Common settings for UniPhier Family */
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#ifndef __CONFIG_UNIPHIER_COMMON_H__
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#define __CONFIG_UNIPHIER_COMMON_H__
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#if defined(CONFIG_MACH_PH1_PRO4)
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#define CONFIG_DDR_NUM_CH0 2
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#define CONFIG_DDR_NUM_CH1 2
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/* Physical start address of SDRAM */
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#define CONFIG_SDRAM0_BASE 0x80000000
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#define CONFIG_SDRAM0_SIZE 0x20000000
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#define CONFIG_SDRAM1_BASE 0xa0000000
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#define CONFIG_SDRAM1_SIZE 0x20000000
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#endif
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#if defined(CONFIG_MACH_PH1_LD4)
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#define CONFIG_DDR_NUM_CH0 1
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#define CONFIG_DDR_NUM_CH1 1
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/* Physical start address of SDRAM */
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#define CONFIG_SDRAM0_BASE 0x80000000
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#define CONFIG_SDRAM0_SIZE 0x10000000
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#define CONFIG_SDRAM1_BASE 0x90000000
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#define CONFIG_SDRAM1_SIZE 0x10000000
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#endif
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#if defined(CONFIG_MACH_PH1_SLD8)
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#define CONFIG_DDR_NUM_CH0 1
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#define CONFIG_DDR_NUM_CH1 1
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/* Physical start address of SDRAM */
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#define CONFIG_SDRAM0_BASE 0x80000000
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#define CONFIG_SDRAM0_SIZE 0x10000000
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#define CONFIG_SDRAM1_BASE 0x90000000
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#define CONFIG_SDRAM1_SIZE 0x10000000
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#endif
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/*
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* Support card address map
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*/
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#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
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# define CONFIG_SUPPORT_CARD_BASE 0x03f00000
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# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
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# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000)
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# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000)
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#endif
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#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
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# define CONFIG_SUPPORT_CARD_BASE 0x08000000
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# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000)
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# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630)
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# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000)
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#endif
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#ifdef CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE
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#define CONFIG_SYS_NS16550_CLK 12288000
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#define CONFIG_SYS_NS16550_REG_SIZE -2
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#endif
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/* TODO: move to Kconfig and device tree */
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#if 0
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#define CONFIG_SYS_NS16550_SERIAL
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#endif
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#define CONFIG_SMC911X
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#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
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#define CONFIG_SMC911X_32_BIT
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#define CONFIG_SYS_MALLOC_F_LEN 0x2000
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/*-----------------------------------------------------------------------
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* MMU and Cache Setting
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*----------------------------------------------------------------------*/
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/* Comment out the following to enable L1 cache */
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/* #define CONFIG_SYS_ICACHE_OFF */
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/* #define CONFIG_SYS_DCACHE_OFF */
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/* Comment out the following to enable L2 cache */
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#define CONFIG_UNIPHIER_L2CACHE_ON
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
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#define CONFIG_TIMESTAMP
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/* FLASH related */
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#define CONFIG_MTD_DEVICE
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/*
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* uncomment the following to disable FLASH related code.
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*/
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/* #define CONFIG_SYS_NO_FLASH */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_MONITOR_BASE 0
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#define CONFIG_SYS_FLASH_BASE 0
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/*
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* flash_toggle does not work for out supoort card.
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* We need to use flash_status_poll.
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*/
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#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
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/* serial console configuration */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_GENERIC_BOARD
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#if !defined(CONFIG_SPL_BUILD)
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#define CONFIG_USE_ARCH_MEMSET
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#define CONFIG_USE_ARCH_MEMCPY
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#endif
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_CMDLINE_EDITING /* add command line history */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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#define CONFIG_CONS_INDEX 1
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/*
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* For NAND booting the environment is embedded in the U-Boot image. Please take
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* look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
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*/
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/* #define CONFIG_ENV_IS_IN_NAND */
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#define CONFIG_ENV_IS_NOWHERE
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET 0x0
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/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
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/* Time clock 1MHz */
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#define CONFIG_SYS_TIMER_RATE 1000000
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/*
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* By default, ARP timeout is 5 sec.
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* The first ARP request does not seem to work.
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* So we need to retry ARP request anyway.
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* We want to shrink the interval until the second ARP request.
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*/
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#define CONFIG_ARP_TIMEOUT 500UL /* 0.5 msec */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_MAX_CHIPS 2
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_NAND_DENALI_ECC_SIZE 1024
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#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
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#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
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#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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/* USB */
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_CMD_FAT
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#define CONFIG_FAT_WRITE
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#define CONFIG_DOS_PARTITION
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_AUTOBOOT_KEYED 1
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#define CONFIG_AUTOBOOT_PROMPT \
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"Press SPACE to abort autoboot in %d seconds\n", bootdelay
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#define CONFIG_AUTOBOOT_DELAY_STR "d"
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#define CONFIG_AUTOBOOT_STOP_STR " "
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/*
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* Network Configuration
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*/
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#define CONFIG_ETHADDR 00:21:83:24:00:00
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#define CONFIG_SERVERIP 192.168.11.1
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#define CONFIG_IPADDR 192.168.11.10
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#define CONFIG_GATEWAYIP 192.168.11.1
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_LOADADDR 0x84000000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_BOOTFILE "fit.itb"
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#define CONFIG_CMDLINE_EDITING /* add command line history */
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#define CONFIG_BOOTCOMMAND "run $bootmode"
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#define CONFIG_ROOTPATH "/nfs/root/path"
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs $bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
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"tftpboot; bootm;"
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#define CONFIG_BOOTARGS " user_debug=0x1f init=/sbin/init"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"image_offset=0x00080000\0" \
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"image_size=0x00f00000\0" \
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"verify=n\0" \
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"norboot=run add_default_bootargs;" \
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"bootm $image_offset\0" \
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"nandboot=run add_default_bootargs;" \
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"nand read $loadaddr $image_offset $image_size;" \
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"bootm\0" \
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"add_default_bootargs=setenv bootargs $bootargs" \
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" console=ttyS0,$baudrate\0" \
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/* Open Firmware flat tree */
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#define CONFIG_OF_LIBFDT
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#define CONFIG_HAVE_ARM_SECURE
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/* Memory Size & Mapping */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE
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#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
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/* Thre is no memory hole */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
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#else
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#define CONFIG_NR_DRAM_BANKS 2
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#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
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#endif
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#define CONFIG_SYS_TEXT_BASE 0x84000000
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#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
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#define CONFIG_SPL_TEXT_BASE 0x00040000
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#endif
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#if defined(CONFIG_MACH_PH1_PRO4)
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#define CONFIG_SPL_TEXT_BASE 0x00100000
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#endif
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#define CONFIG_BOARD_POSTCLK_INIT
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#endif
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#define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000)
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#define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000)
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#define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000)
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000
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#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
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