mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 18:59:44 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
463 lines
12 KiB
C
463 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2016 Google, Inc
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/scu_ast2500.h>
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#include <dm/lists.h>
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#include <dt-bindings/clock/ast2500-scu.h>
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/*
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* MAC Clock Delay settings, taken from Aspeed SDK
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*/
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#define RGMII_TXCLK_ODLY 8
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#define RMII_RXCLK_IDLY 2
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/*
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* TGMII Clock Duty constants, taken from Aspeed SDK
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*/
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#define RGMII2_TXCK_DUTY 0x66
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#define RGMII1_TXCK_DUTY 0x64
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#define D2PLL_DEFAULT_RATE (250 * 1000 * 1000)
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Clock divider/multiplier configuration struct.
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* For H-PLL and M-PLL the formula is
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* (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
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* M - Numerator
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* N - Denumerator
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* P - Post Divider
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* They have the same layout in their control register.
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*
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* D-PLL and D2-PLL have extra divider (OD + 1), which is not
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* yet needed and ignored by clock configurations.
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*/
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struct ast2500_div_config {
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unsigned int num;
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unsigned int denum;
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unsigned int post_div;
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};
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/*
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* Get the rate of the M-PLL clock from input clock frequency and
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* the value of the M-PLL Parameter Register.
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*/
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static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
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{
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const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
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const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
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>> SCU_MPLL_DENUM_SHIFT;
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const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
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>> SCU_MPLL_POST_SHIFT;
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return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
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}
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/*
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* Get the rate of the H-PLL clock from input clock frequency and
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* the value of the H-PLL Parameter Register.
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*/
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static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
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{
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const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
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const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
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>> SCU_HPLL_DENUM_SHIFT;
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const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
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>> SCU_HPLL_POST_SHIFT;
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return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
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}
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static ulong ast2500_get_clkin(struct ast2500_scu *scu)
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{
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return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ
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? 25 * 1000 * 1000 : 24 * 1000 * 1000;
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}
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/**
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* Get current rate or uart clock
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*
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* @scu SCU registers
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* @uart_index UART index, 1-5
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*
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* @return current setting for uart clock rate
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*/
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static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index)
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{
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/*
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* ast2500 datasheet is very confusing when it comes to UART clocks,
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* especially when CLKIN = 25 MHz. The settings are in
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* different registers and it is unclear how they interact.
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*
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* This has only been tested with default settings and CLKIN = 24 MHz.
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*/
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ulong uart_clkin;
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if (readl(&scu->misc_ctrl2) &
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(1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT)))
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uart_clkin = 192 * 1000 * 1000;
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else
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uart_clkin = 24 * 1000 * 1000;
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if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13)
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uart_clkin /= 13;
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return uart_clkin;
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}
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static ulong ast2500_clk_get_rate(struct clk *clk)
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{
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struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
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ulong clkin = ast2500_get_clkin(priv->scu);
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ulong rate;
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switch (clk->id) {
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case PLL_HPLL:
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case ARMCLK:
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/*
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* This ignores dynamic/static slowdown of ARMCLK and may
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* be inaccurate.
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*/
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rate = ast2500_get_hpll_rate(clkin,
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readl(&priv->scu->h_pll_param));
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break;
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case MCLK_DDR:
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rate = ast2500_get_mpll_rate(clkin,
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readl(&priv->scu->m_pll_param));
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break;
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case BCLK_PCLK:
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{
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ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
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& SCU_PCLK_DIV_MASK)
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>> SCU_PCLK_DIV_SHIFT);
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rate = ast2500_get_hpll_rate(clkin,
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readl(&priv->
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scu->h_pll_param));
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rate = rate / apb_div;
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}
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break;
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case PCLK_UART1:
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rate = ast2500_get_uart_clk_rate(priv->scu, 1);
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break;
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case PCLK_UART2:
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rate = ast2500_get_uart_clk_rate(priv->scu, 2);
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break;
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case PCLK_UART3:
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rate = ast2500_get_uart_clk_rate(priv->scu, 3);
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break;
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case PCLK_UART4:
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rate = ast2500_get_uart_clk_rate(priv->scu, 4);
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break;
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case PCLK_UART5:
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rate = ast2500_get_uart_clk_rate(priv->scu, 5);
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break;
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default:
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return -ENOENT;
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}
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return rate;
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}
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/*
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* @input_rate - the rate of input clock in Hz
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* @requested_rate - desired output rate in Hz
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* @div - this is an IN/OUT parameter, at input all fields of the config
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* need to be set to their maximum allowed values.
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* The result (the best config we could find), would also be returned
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* in this structure.
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*
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* @return The clock rate, when the resulting div_config is used.
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*/
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static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate,
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struct ast2500_div_config *cfg)
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{
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/*
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* The assumption is that kHz precision is good enough and
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* also enough to avoid overflow when multiplying.
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*/
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const ulong input_rate_khz = input_rate / 1000;
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const ulong rate_khz = requested_rate / 1000;
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const struct ast2500_div_config max_vals = *cfg;
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struct ast2500_div_config it = { 0, 0, 0 };
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ulong delta = rate_khz;
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ulong new_rate_khz = 0;
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for (; it.denum <= max_vals.denum; ++it.denum) {
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for (it.post_div = 0; it.post_div <= max_vals.post_div;
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++it.post_div) {
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it.num = (rate_khz * (it.post_div + 1) / input_rate_khz)
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* (it.denum + 1);
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if (it.num > max_vals.num)
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continue;
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new_rate_khz = (input_rate_khz
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* ((it.num + 1) / (it.denum + 1)))
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/ (it.post_div + 1);
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/* Keep the rate below requested one. */
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if (new_rate_khz > rate_khz)
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continue;
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if (new_rate_khz - rate_khz < delta) {
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delta = new_rate_khz - rate_khz;
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*cfg = it;
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if (delta == 0)
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return new_rate_khz * 1000;
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}
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}
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}
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return new_rate_khz * 1000;
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}
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static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)
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{
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ulong clkin = ast2500_get_clkin(scu);
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u32 mpll_reg;
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struct ast2500_div_config div_cfg = {
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.num = (SCU_MPLL_NUM_MASK >> SCU_MPLL_NUM_SHIFT),
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.denum = (SCU_MPLL_DENUM_MASK >> SCU_MPLL_DENUM_SHIFT),
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.post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT),
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};
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ast2500_calc_clock_config(clkin, rate, &div_cfg);
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mpll_reg = readl(&scu->m_pll_param);
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mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK
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| SCU_MPLL_DENUM_MASK);
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mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT)
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| (div_cfg.num << SCU_MPLL_NUM_SHIFT)
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| (div_cfg.denum << SCU_MPLL_DENUM_SHIFT);
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ast_scu_unlock(scu);
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writel(mpll_reg, &scu->m_pll_param);
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ast_scu_lock(scu);
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return ast2500_get_mpll_rate(clkin, mpll_reg);
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}
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static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index)
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{
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ulong clkin = ast2500_get_clkin(scu);
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ulong hpll_rate = ast2500_get_hpll_rate(clkin,
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readl(&scu->h_pll_param));
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ulong required_rate;
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u32 hwstrap;
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u32 divisor;
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u32 reset_bit;
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u32 clkstop_bit;
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/*
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* According to data sheet, for 10/100 mode the MAC clock frequency
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* should be at least 25MHz and for 1000 mode at least 100MHz
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*/
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hwstrap = readl(&scu->hwstrap);
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if (hwstrap & (SCU_HWSTRAP_MAC1_RGMII | SCU_HWSTRAP_MAC2_RGMII))
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required_rate = 100 * 1000 * 1000;
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else
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required_rate = 25 * 1000 * 1000;
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divisor = hpll_rate / required_rate;
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if (divisor < 4) {
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/* Clock can't run fast enough, but let's try anyway */
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debug("MAC clock too slow\n");
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divisor = 4;
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} else if (divisor > 16) {
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/* Can't slow down the clock enough, but let's try anyway */
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debug("MAC clock too fast\n");
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divisor = 16;
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}
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switch (index) {
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case 1:
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reset_bit = SCU_SYSRESET_MAC1;
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clkstop_bit = SCU_CLKSTOP_MAC1;
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break;
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case 2:
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reset_bit = SCU_SYSRESET_MAC2;
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clkstop_bit = SCU_CLKSTOP_MAC2;
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break;
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default:
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return -EINVAL;
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}
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ast_scu_unlock(scu);
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clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK,
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((divisor - 2) / 2) << SCU_MACCLK_SHIFT);
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/*
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* Disable MAC, start its clock and re-enable it.
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* The procedure and the delays (100us & 10ms) are
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* specified in the datasheet.
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*/
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setbits_le32(&scu->sysreset_ctrl1, reset_bit);
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udelay(100);
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clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);
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mdelay(10);
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clrbits_le32(&scu->sysreset_ctrl1, reset_bit);
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writel((RGMII2_TXCK_DUTY << SCU_CLKDUTY_RGMII2TXCK_SHIFT)
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| (RGMII1_TXCK_DUTY << SCU_CLKDUTY_RGMII1TXCK_SHIFT),
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&scu->clk_duty_sel);
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ast_scu_lock(scu);
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return required_rate;
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}
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static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)
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{
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/*
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* The values and the meaning of the next three
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* parameters are undocumented. Taken from Aspeed SDK.
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*/
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const u32 d2_pll_ext_param = 0x2c;
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const u32 d2_pll_sip = 0x11;
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const u32 d2_pll_sic = 0x18;
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u32 clk_delay_settings =
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(RMII_RXCLK_IDLY << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
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| (RMII_RXCLK_IDLY << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
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| (RGMII_TXCLK_ODLY << SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
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| (RGMII_TXCLK_ODLY << SCU_MICDS_MAC2RGMII_TXDLY_SHIFT);
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struct ast2500_div_config div_cfg = {
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.num = SCU_D2PLL_NUM_MASK >> SCU_D2PLL_NUM_SHIFT,
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.denum = SCU_D2PLL_DENUM_MASK >> SCU_D2PLL_DENUM_SHIFT,
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.post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT,
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};
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ulong clkin = ast2500_get_clkin(scu);
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ulong new_rate;
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ast_scu_unlock(scu);
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writel((d2_pll_ext_param << SCU_D2PLL_EXT1_PARAM_SHIFT)
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| SCU_D2PLL_EXT1_OFF
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| SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]);
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/*
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* Select USB2.0 port1 PHY clock as a clock source for GCRT.
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* This would disconnect it from D2-PLL.
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*/
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clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF,
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SCU_MISC_GCRT_USB20CLK);
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new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg);
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writel((d2_pll_sip << SCU_D2PLL_SIP_SHIFT)
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| (d2_pll_sic << SCU_D2PLL_SIC_SHIFT)
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| (div_cfg.num << SCU_D2PLL_NUM_SHIFT)
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| (div_cfg.denum << SCU_D2PLL_DENUM_SHIFT)
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| (div_cfg.post_div << SCU_D2PLL_POST_SHIFT),
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&scu->d2_pll_param);
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clrbits_le32(&scu->d2_pll_ext_param[0],
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SCU_D2PLL_EXT1_OFF | SCU_D2PLL_EXT1_RESET);
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clrsetbits_le32(&scu->misc_ctrl2,
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SCU_MISC2_RGMII_HPLL | SCU_MISC2_RMII_MPLL
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| SCU_MISC2_RGMII_CLKDIV_MASK |
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SCU_MISC2_RMII_CLKDIV_MASK,
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(4 << SCU_MISC2_RMII_CLKDIV_SHIFT));
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writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay);
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writel(clk_delay_settings, &scu->mac_clk_delay_100M);
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writel(clk_delay_settings, &scu->mac_clk_delay_10M);
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ast_scu_lock(scu);
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return new_rate;
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}
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static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
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{
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struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
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ulong new_rate;
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switch (clk->id) {
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case PLL_MPLL:
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case MCLK_DDR:
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new_rate = ast2500_configure_ddr(priv->scu, rate);
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break;
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case PLL_D2PLL:
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new_rate = ast2500_configure_d2pll(priv->scu, rate);
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break;
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default:
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return -ENOENT;
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}
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return new_rate;
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}
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static int ast2500_clk_enable(struct clk *clk)
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{
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struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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/*
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* For MAC clocks the clock rate is
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* configured based on whether RGMII or RMII mode has been selected
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* through hardware strapping.
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*/
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case PCLK_MAC1:
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ast2500_configure_mac(priv->scu, 1);
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break;
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case PCLK_MAC2:
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ast2500_configure_mac(priv->scu, 2);
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break;
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case PLL_D2PLL:
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ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
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default:
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return -ENOENT;
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}
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return 0;
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}
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struct clk_ops ast2500_clk_ops = {
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.get_rate = ast2500_clk_get_rate,
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.set_rate = ast2500_clk_set_rate,
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.enable = ast2500_clk_enable,
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};
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static int ast2500_clk_probe(struct udevice *dev)
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{
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struct ast2500_clk_priv *priv = dev_get_priv(dev);
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priv->scu = devfdt_get_addr_ptr(dev);
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if (IS_ERR(priv->scu))
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return PTR_ERR(priv->scu);
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return 0;
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}
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static int ast2500_clk_bind(struct udevice *dev)
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{
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int ret;
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/* The reset driver does not have a device node, so bind it here */
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ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev);
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if (ret)
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debug("Warning: No reset driver: ret=%d\n", ret);
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return 0;
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}
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static const struct udevice_id ast2500_clk_ids[] = {
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{ .compatible = "aspeed,ast2500-scu" },
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{ }
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};
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U_BOOT_DRIVER(aspeed_ast2500_scu) = {
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.name = "aspeed_ast2500_scu",
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.id = UCLASS_CLK,
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.of_match = ast2500_clk_ids,
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.priv_auto_alloc_size = sizeof(struct ast2500_clk_priv),
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.ops = &ast2500_clk_ops,
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.bind = ast2500_clk_bind,
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.probe = ast2500_clk_probe,
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};
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