mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-21 07:01:57 +00:00
c0f4756216
Currently CONFIG_SPL_TEXT_BASE and CONFIG_SYS_TEXT_BASE addresses are manually increased by 0x1000 due to .bootpg section. This section has size of 0x1000 bytes and is manually put by linker script before .text section (and therefore before base address) when CONFIG_SYS_MPC85XX_NO_RESETVEC is set. Due to this fact lot of other config options are manually increased by 0x1000 value to make correct layout. Note that entry point is not on CONFIG_SPL_TEXT_BASE (image+0x1000) but it is really on address CONFIG_SPL_TEXT_BASE-0x1000 (means at the start of the image). Cleanup handling of .bootpg section when CONFIG_SYS_MPC85XX_NO_RESETVEC is set. Put .bootpg code directly into .text section and move text base address to the start of .bootpg code. And finally remove +0x1000 value from lot of config options. With this removal custom PHDRS is not used anymore, so remove it too. After this change entry point would be at CONFIG_SPL_TEXT_BASE and not at address -0x1000 anymore. Tested on P2020 board with SPL and proper U-Boot. Signed-off-by: Pali Rohár <pali@kernel.org>
130 lines
3.6 KiB
Text
130 lines
3.6 KiB
Text
CONFIG_PPC=y
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CONFIG_SYS_TEXT_BASE=0x00200000
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_OFFSET=0x100000
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CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
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CONFIG_SPL_TEXT_BASE=0xFFFD8000
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CONFIG_VID=y
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CONFIG_VID_FLS_ENV="t208xrdb_vdd_mv"
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CONFIG_VOL_MONITOR_IR36021_READ=y
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CONFIG_VOL_MONITOR_IR36021_SET=y
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CONFIG_SPL_MMC=y
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CONFIG_SPL_SERIAL=y
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CONFIG_SPL_DRIVERS_MISC=y
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CONFIG_SPL=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_T2080RDB=y
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CONFIG_T2080RDB_REV_D=y
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CONFIG_SYS_MEMTEST_START=0x00200000
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CONFIG_SYS_MEMTEST_END=0x00400000
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CONFIG_MP=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_RAMBOOT_PBL=y
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CONFIG_SYS_FSL_PBL_PBI="board/freescale/t208xrdb/t2080_pbi.cfg"
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CONFIG_SYS_FSL_PBL_RCW="board/freescale/t208xrdb/t2080_sd_rcw.cfg"
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CONFIG_BOOTDELAY=10
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CONFIG_USE_BOOTCOMMAND=y
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CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
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CONFIG_ARCH_MISC_INIT=y
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CONFIG_BOARD_EARLY_INIT_R=y
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# CONFIG_SPL_FRAMEWORK is not set
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CONFIG_SPL_MAX_SIZE=0x28000
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CONFIG_SPL_PAD_TO=0x40000
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CONFIG_SPL_MMC_BOOT=y
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CONFIG_SPL_FSL_PBL=y
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CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE=y
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CONFIG_SPL_FLUSH_IMAGE=y
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CONFIG_SPL_SKIP_RELOCATE=y
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CONFIG_SPL_GD_ADDR=0xfffc8000
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CONFIG_SPL_RELOC_STACK=0xfffd8000
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CONFIG_SPL_RELOC_MALLOC=y
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CONFIG_SPL_RELOC_MALLOC_ADDR=0xfffcb000
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CONFIG_SPL_RELOC_MALLOC_SIZE=0xc800
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CONFIG_SPL_ENV_SUPPORT=y
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CONFIG_SPL_I2C=y
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CONFIG_SPL_MPC8XXX_INIT_DDR=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PBSIZE=276
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CONFIG_CMD_IMLS=y
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CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
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CONFIG_CMD_MEMTEST=y
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CONFIG_SYS_ALT_MEMTEST=y
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CONFIG_CMD_DM=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:1m(uboot),5m(kernel),128k(dtb),-(user)"
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# CONFIG_CMD_IRQ is not set
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_USE_BOOTFILE=y
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CONFIG_BOOTFILE="uImage"
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CONFIG_USE_ETHPRIME=y
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CONFIG_ETHPRIME="FM1@DTSEC3"
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CONFIG_DM=y
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CONFIG_SYS_SATA_MAX_DEVICE=2
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CONFIG_FSL_CAAM=y
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CONFIG_DDR_CLK_FREQ=133330000
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CONFIG_DDR_ECC=y
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CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
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CONFIG_DM_I2C=y
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CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
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CONFIG_SYS_I2C_FSL=y
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CONFIG_SYS_FSL_I2C_OFFSET=0x118000
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CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
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CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
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CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
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CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
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CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
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CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
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CONFIG_SYS_I2C_EEPROM_ADDR=0x50
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_SPEED=10000000
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_CORTINA=y
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CONFIG_SYS_CORTINA_FW_IN_MMC=y
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CONFIG_CORTINA_FW_ADDR=0x114000
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CONFIG_PHY_REALTEK=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_E1000=y
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CONFIG_FMAN_ENET=y
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CONFIG_SYS_FMAN_FW_ADDR=0x104000
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CONFIG_MII=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCIE_FSL=y
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CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_DS1307=y
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_FSL_ESPI=y
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CONFIG_USB=y
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CONFIG_USB_EHCI_FSL=y
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CONFIG_USB_STORAGE=y
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CONFIG_ADDR_MAP=y
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CONFIG_SYS_NUM_ADDR_MAP=64
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