mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 16:39:35 +00:00
4e1f81d4eb
These nodes are not parsed by U-Boot for now, but syncing device trees with Linux is helpful for easier diffing. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
158 lines
3.2 KiB
Text
158 lines
3.2 KiB
Text
/*
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* Device Tree Source for UniPhier PH1-sLD8 SoC
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*
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* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+ X11
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*/
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/include/ "uniphier-common32.dtsi"
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/ {
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compatible = "socionext,ph1-sld8";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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next-level-cache = <&l2>;
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};
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};
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clocks {
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arm_timer_clk: arm_timer_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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uart_clk: uart_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <80000000>;
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};
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iobus_clk: iobus_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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};
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};
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};
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&soc {
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
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interrupts = <0 174 4>, <0 175 4>;
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cache-unified;
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cache-size = <(256 * 1024)>;
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cache-sets = <256>;
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cache-line-size = <128>;
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cache-level = <2>;
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};
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i2c0: i2c@58400000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58400000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58480000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58480000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 42 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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/* chip-internal connection for DMD */
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i2c2: i2c@58500000 {
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compatible = "socionext,uniphier-i2c";
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reg = <0x58500000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clocks = <&iobus_clk>;
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clock-frequency = <400000>;
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};
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i2c3: i2c@58580000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58580000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 44 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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usb0: usb@5a800100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a800100 0x100>;
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interrupts = <0 80 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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};
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usb1: usb@5a810100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a810100 0x100>;
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interrupts = <0 81 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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};
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usb2: usb@5a820100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a820100 0x100>;
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interrupts = <0 82 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb2>;
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};
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};
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&serial0 {
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clock-frequency = <80000000>;
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};
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&serial1 {
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clock-frequency = <80000000>;
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};
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&serial2 {
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clock-frequency = <80000000>;
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};
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&serial3 {
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interrupts = <0 29 4>;
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clock-frequency = <80000000>;
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};
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&pinctrl {
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compatible = "socionext,ph1-sld8-pinctrl", "syscon";
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};
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