mirror of
https://github.com/AsahiLinux/u-boot
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1332a781e1
Xilinx is using standard mtd partition layout for quite a long time. It is used for testing purpose on evaluation boards. Also #address/size-cells shouldn't be present without nodes which should use them that's why move them from zynq-7000.dtsi to nand/nor nodes directly. The patch was tested on zc706 and zedboard(with also increasing max frequency and rx bus width). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/4c3348981bba32d3892194420d78fe8621c47534.1698837725.git.michal.simek@amd.com
372 lines
6.1 KiB
Text
372 lines
6.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011 - 2015 Xilinx
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* Copyright (C) 2012 National Instruments Corp.
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*/
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/dts-v1/;
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#include "zynq-7000.dtsi"
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/ {
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model = "Xilinx ZC706 board";
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compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
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aliases {
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ethernet0 = &gem0;
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i2c0 = &i2c0;
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serial0 = &uart1;
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spi0 = &qspi;
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mmc0 = &sdhci0;
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nvmem0 = &eeprom;
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rtc0 = &rtc;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x40000000>;
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};
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chosen {
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bootargs = "";
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stdout-path = "serial0:115200n8";
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};
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usb_phy0: phy0 {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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};
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&clkc {
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ps-clk-frequency = <33333333>;
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};
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&gem0 {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem0_default>;
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ethernet_phy: ethernet-phy@7 {
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reg = <7>;
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device_type = "ethernet-phy";
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};
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};
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&gpio0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio0_default>;
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0_default>;
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i2c-mux@74 {
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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si570: clock-generator@5d {
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#clock-cells = <0>;
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compatible = "silabs,si570";
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temperature-stability = <50>;
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reg = <0x5d>;
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factory-fout = <156250000>;
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clock-frequency = <148500000>;
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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adv7511: hdmi-tx@39 {
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compatible = "adi,adv7511";
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reg = <0x39>;
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adi,input-depth = <8>;
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adi,input-colorspace = "yuv422";
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adi,input-clock = "1x";
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adi,input-style = <3>;
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adi,input-justification = "evenly";
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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eeprom: eeprom@54 {
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compatible = "atmel,24c08";
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reg = <0x54>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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gpio@21 {
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compatible = "ti,tca6416";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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rtc: rtc@51 {
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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};
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};
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i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <7>;
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ucd90120@65 {
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compatible = "ti,ucd90120";
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reg = <0x65>;
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};
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};
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};
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};
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&pinctrl0 {
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pinctrl_gem0_default: gem0-default {
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mux {
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function = "ethernet0";
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groups = "ethernet0_0_grp";
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};
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conf {
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groups = "ethernet0_0_grp";
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slew-rate = <0>;
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power-source = <4>;
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};
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conf-rx {
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pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
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bias-high-impedance;
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low-power-disable;
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};
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conf-tx {
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pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
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low-power-enable;
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bias-disable;
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};
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mux-mdio {
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function = "mdio0";
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groups = "mdio0_0_grp";
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};
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conf-mdio {
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groups = "mdio0_0_grp";
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slew-rate = <0>;
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power-source = <1>;
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bias-disable;
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};
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};
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pinctrl_gpio0_default: gpio0-default {
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mux {
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function = "gpio0";
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groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
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};
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conf {
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groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
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slew-rate = <0>;
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power-source = <1>;
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};
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conf-pull-up {
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pins = "MIO46", "MIO47";
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bias-pull-up;
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};
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conf-pull-none {
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pins = "MIO7";
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bias-disable;
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};
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};
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pinctrl_i2c0_default: i2c0-default {
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mux {
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groups = "i2c0_10_grp";
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function = "i2c0";
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};
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conf {
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groups = "i2c0_10_grp";
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bias-pull-up;
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slew-rate = <0>;
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power-source = <1>;
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};
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};
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pinctrl_sdhci0_default: sdhci0-default {
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mux {
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groups = "sdio0_2_grp";
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function = "sdio0";
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};
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conf {
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groups = "sdio0_2_grp";
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slew-rate = <0>;
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power-source = <1>;
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bias-disable;
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};
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mux-cd {
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groups = "gpio0_14_grp";
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function = "sdio0_cd";
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};
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conf-cd {
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groups = "gpio0_14_grp";
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bias-high-impedance;
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bias-pull-up;
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slew-rate = <0>;
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power-source = <1>;
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};
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mux-wp {
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groups = "gpio0_15_grp";
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function = "sdio0_wp";
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};
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conf-wp {
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groups = "gpio0_15_grp";
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bias-high-impedance;
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bias-pull-up;
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slew-rate = <0>;
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power-source = <1>;
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};
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};
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pinctrl_uart1_default: uart1-default {
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mux {
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groups = "uart1_10_grp";
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function = "uart1";
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};
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conf {
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groups = "uart1_10_grp";
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slew-rate = <0>;
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power-source = <1>;
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};
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conf-rx {
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pins = "MIO49";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO48";
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bias-disable;
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};
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};
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pinctrl_usb0_default: usb0-default {
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mux {
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groups = "usb0_0_grp";
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function = "usb0";
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};
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conf {
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groups = "usb0_0_grp";
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slew-rate = <0>;
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power-source = <1>;
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};
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conf-rx {
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pins = "MIO29", "MIO31", "MIO36";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
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"MIO35", "MIO37", "MIO38", "MIO39";
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bias-disable;
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};
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};
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};
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&qspi {
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bootph-all;
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status = "okay";
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num-cs = <2>;
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flash@0 {
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compatible = "n25q128a11", "jedec,spi-nor";
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reg = <0>, <1>;
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parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <50000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "qspi-fsbl-uboot";
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reg = <0x0 0x100000>;
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};
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partition@100000 {
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label = "qspi-linux";
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reg = <0x100000 0x500000>;
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};
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partition@600000 {
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label = "qspi-device-tree";
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reg = <0x600000 0x20000>;
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};
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partition@620000 {
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label = "qspi-rootfs";
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reg = <0x620000 0x5e0000>;
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};
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partition@c00000 {
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label = "qspi-bitstream";
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reg = <0xc00000 0x400000>;
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};
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};
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};
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};
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&sdhci0 {
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bootph-all;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhci0_default>;
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};
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&uart1 {
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bootph-all;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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&usb0 {
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status = "okay";
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dr_mode = "host";
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usb-phy = <&usb_phy0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_default>;
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};
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&watchdog0 {
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reset-on-timeout;
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};
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