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19a25f672c
This is common to all SPI drivers and specifies a structure used by the uclass. It makes more sense to define it in the uclass. Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Simon Glass <sjg@chromium.org>
365 lines
10 KiB
C
365 lines
10 KiB
C
/*
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* NVIDIA Tegra SPI-SLINK controller
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*
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* Copyright (c) 2010-2013 NVIDIA Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <spi.h>
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#include <fdtdec.h>
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#include "tegra_spi.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* COMMAND */
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#define SLINK_CMD_ENB (1 << 31)
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#define SLINK_CMD_GO (1 << 30)
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#define SLINK_CMD_M_S (1 << 28)
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#define SLINK_CMD_CK_SDA (1 << 21)
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#define SLINK_CMD_CS_POL (1 << 13)
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#define SLINK_CMD_CS_VAL (1 << 12)
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#define SLINK_CMD_CS_SOFT (1 << 11)
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#define SLINK_CMD_BIT_LENGTH (1 << 4)
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#define SLINK_CMD_BIT_LENGTH_MASK 0x0000001F
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/* COMMAND2 */
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#define SLINK_CMD2_TXEN (1 << 30)
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#define SLINK_CMD2_RXEN (1 << 31)
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#define SLINK_CMD2_SS_EN (1 << 18)
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#define SLINK_CMD2_SS_EN_SHIFT 18
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#define SLINK_CMD2_SS_EN_MASK 0x000C0000
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#define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 << 17)
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/* STATUS */
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#define SLINK_STAT_BSY (1 << 31)
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#define SLINK_STAT_RDY (1 << 30)
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#define SLINK_STAT_ERR (1 << 29)
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#define SLINK_STAT_RXF_FLUSH (1 << 27)
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#define SLINK_STAT_TXF_FLUSH (1 << 26)
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#define SLINK_STAT_RXF_OVF (1 << 25)
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#define SLINK_STAT_TXF_UNR (1 << 24)
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#define SLINK_STAT_RXF_EMPTY (1 << 23)
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#define SLINK_STAT_RXF_FULL (1 << 22)
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#define SLINK_STAT_TXF_EMPTY (1 << 21)
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#define SLINK_STAT_TXF_FULL (1 << 20)
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#define SLINK_STAT_TXF_OVF (1 << 19)
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#define SLINK_STAT_RXF_UNR (1 << 18)
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#define SLINK_STAT_CUR_BLKCNT (1 << 15)
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/* STATUS2 */
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#define SLINK_STAT2_RXF_FULL_CNT (1 << 16)
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#define SLINK_STAT2_TXF_FULL_CNT (1 << 0)
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#define SPI_TIMEOUT 1000
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#define TEGRA_SPI_MAX_FREQ 52000000
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struct spi_regs {
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u32 command; /* SLINK_COMMAND_0 register */
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u32 command2; /* SLINK_COMMAND2_0 reg */
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u32 status; /* SLINK_STATUS_0 register */
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u32 reserved; /* Reserved offset 0C */
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u32 mas_data; /* SLINK_MAS_DATA_0 reg */
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u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */
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u32 dma_ctl; /* SLINK_DMA_CTL_0 register */
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u32 status2; /* SLINK_STATUS2_0 reg */
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u32 rsvd[56]; /* 0x20 to 0xFF reserved */
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u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */
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u32 rsvd2[31]; /* 0x104 to 0x17F reserved */
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u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */
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};
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struct tegra30_spi_priv {
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struct spi_regs *regs;
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unsigned int freq;
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unsigned int mode;
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int periph_id;
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int valid;
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int last_transaction_us;
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};
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struct tegra_spi_slave {
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struct spi_slave slave;
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struct tegra30_spi_priv *ctrl;
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};
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static int tegra30_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct tegra_spi_platdata *plat = bus->platdata;
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const void *blob = gd->fdt_blob;
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int node = bus->of_offset;
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plat->base = fdtdec_get_addr(blob, node, "reg");
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plat->periph_id = clock_decode_periph_id(blob, node);
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if (plat->periph_id == PERIPH_ID_NONE) {
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debug("%s: could not decode periph id %d\n", __func__,
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plat->periph_id);
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return -FDT_ERR_NOTFOUND;
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}
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/* Use 500KHz as a suitable default */
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plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
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500000);
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plat->deactivate_delay_us = fdtdec_get_int(blob, node,
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"spi-deactivate-delay", 0);
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debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
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__func__, plat->base, plat->periph_id, plat->frequency,
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plat->deactivate_delay_us);
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return 0;
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}
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static int tegra30_spi_probe(struct udevice *bus)
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{
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struct tegra_spi_platdata *plat = dev_get_platdata(bus);
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struct tegra30_spi_priv *priv = dev_get_priv(bus);
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priv->regs = (struct spi_regs *)plat->base;
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priv->last_transaction_us = timer_get_us();
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priv->freq = plat->frequency;
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priv->periph_id = plat->periph_id;
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return 0;
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}
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static int tegra30_spi_claim_bus(struct udevice *bus)
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{
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struct tegra30_spi_priv *priv = dev_get_priv(bus);
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struct spi_regs *regs = priv->regs;
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u32 reg;
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/* Change SPI clock to correct frequency, PLLP_OUT0 source */
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clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
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priv->freq);
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/* Clear stale status here */
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reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
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SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF;
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writel(reg, ®s->status);
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debug("%s: STATUS = %08x\n", __func__, readl(®s->status));
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/* Set master mode and sw controlled CS */
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reg = readl(®s->command);
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reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
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writel(reg, ®s->command);
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debug("%s: COMMAND = %08x\n", __func__, readl(®s->command));
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return 0;
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}
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static void spi_cs_activate(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
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struct tegra30_spi_priv *priv = dev_get_priv(bus);
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/* If it's too soon to do another transaction, wait */
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if (pdata->deactivate_delay_us &&
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priv->last_transaction_us) {
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ulong delay_us; /* The delay completed so far */
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delay_us = timer_get_us() - priv->last_transaction_us;
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if (delay_us < pdata->deactivate_delay_us)
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udelay(pdata->deactivate_delay_us - delay_us);
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}
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/* CS is negated on Tegra, so drive a 1 to get a 0 */
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setbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
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}
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static void spi_cs_deactivate(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
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struct tegra30_spi_priv *priv = dev_get_priv(bus);
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/* CS is negated on Tegra, so drive a 0 to get a 1 */
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clrbits_le32(&priv->regs->command, SLINK_CMD_CS_VAL);
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/* Remember time of this transaction so we can honour the bus delay */
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if (pdata->deactivate_delay_us)
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priv->last_transaction_us = timer_get_us();
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}
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static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *data_out, void *data_in,
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unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct tegra30_spi_priv *priv = dev_get_priv(bus);
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struct spi_regs *regs = priv->regs;
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u32 reg, tmpdout, tmpdin = 0;
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const u8 *dout = data_out;
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u8 *din = data_in;
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int num_bytes;
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int ret;
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debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
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__func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
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if (bitlen % 8)
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return -1;
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num_bytes = bitlen / 8;
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ret = 0;
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reg = readl(®s->status);
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writel(reg, ®s->status); /* Clear all SPI events via R/W */
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debug("%s entry: STATUS = %08x\n", __func__, reg);
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reg = readl(®s->status2);
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writel(reg, ®s->status2); /* Clear all STATUS2 events via R/W */
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debug("%s entry: STATUS2 = %08x\n", __func__, reg);
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debug("%s entry: COMMAND = %08x\n", __func__, readl(®s->command));
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clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK,
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SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
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(spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT));
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debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2));
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(dev);
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/* handle data in 32-bit chunks */
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while (num_bytes > 0) {
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int bytes;
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int is_read = 0;
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int tm, i;
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tmpdout = 0;
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bytes = (num_bytes > 4) ? 4 : num_bytes;
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if (dout != NULL) {
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for (i = 0; i < bytes; ++i)
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tmpdout = (tmpdout << 8) | dout[i];
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dout += bytes;
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}
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num_bytes -= bytes;
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clrsetbits_le32(®s->command, SLINK_CMD_BIT_LENGTH_MASK,
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bytes * 8 - 1);
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writel(tmpdout, ®s->tx_fifo);
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setbits_le32(®s->command, SLINK_CMD_GO);
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/*
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* Wait for SPI transmit FIFO to empty, or to time out.
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* The RX FIFO status will be read and cleared last
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*/
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for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
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u32 status;
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status = readl(®s->status);
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/* We can exit when we've had both RX and TX activity */
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if (is_read && (status & SLINK_STAT_TXF_EMPTY))
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break;
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if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) !=
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SLINK_STAT_RDY)
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tm++;
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else if (!(status & SLINK_STAT_RXF_EMPTY)) {
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tmpdin = readl(®s->rx_fifo);
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is_read = 1;
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/* swap bytes read in */
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if (din != NULL) {
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for (i = bytes - 1; i >= 0; --i) {
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din[i] = tmpdin & 0xff;
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tmpdin >>= 8;
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}
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din += bytes;
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}
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}
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}
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if (tm >= SPI_TIMEOUT)
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ret = tm;
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/* clear ACK RDY, etc. bits */
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writel(readl(®s->status), ®s->status);
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}
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(dev);
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debug("%s: transfer ended. Value=%08x, status = %08x\n",
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__func__, tmpdin, readl(®s->status));
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if (ret) {
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printf("%s: timeout during SPI transfer, tm %d\n",
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__func__, ret);
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return -1;
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}
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return 0;
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}
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static int tegra30_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct tegra_spi_platdata *plat = bus->platdata;
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struct tegra30_spi_priv *priv = dev_get_priv(bus);
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if (speed > plat->frequency)
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speed = plat->frequency;
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priv->freq = speed;
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debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
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return 0;
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}
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static int tegra30_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct tegra30_spi_priv *priv = dev_get_priv(bus);
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priv->mode = mode;
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debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
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return 0;
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}
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static const struct dm_spi_ops tegra30_spi_ops = {
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.claim_bus = tegra30_spi_claim_bus,
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.xfer = tegra30_spi_xfer,
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.set_speed = tegra30_spi_set_speed,
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.set_mode = tegra30_spi_set_mode,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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*/
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};
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static const struct udevice_id tegra30_spi_ids[] = {
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{ .compatible = "nvidia,tegra20-slink" },
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{ }
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};
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U_BOOT_DRIVER(tegra30_spi) = {
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.name = "tegra20_slink",
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.id = UCLASS_SPI,
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.of_match = tegra30_spi_ids,
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.ops = &tegra30_spi_ops,
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.ofdata_to_platdata = tegra30_spi_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
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.priv_auto_alloc_size = sizeof(struct tegra30_spi_priv),
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.probe = tegra30_spi_probe,
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};
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