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https://github.com/AsahiLinux/u-boot
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6c317fedc7
Introduce BSH SystemMaster (SMM) S2 board family, which consists of: iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. Add support for iMX8MN BSH SMM S2 board: - 256 MiB DDR3 RAM - 512MiB Nand - USBOTG1 peripheral - fastboot. - 100Mbit Ethernet Add support for iMX8MN BSH SMM S2 PRO board: - 512 MiB DDR3 RAM - 8 GiB eMMC - USBOTG1 peripheral - fastboot. - 100Mbit Ethernet Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
80 lines
2.3 KiB
Text
80 lines
2.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 Collabora Ltd.
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* Copyright 2021 BSH Hausgeraete GmbH
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*/
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/dts-v1/;
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#include "imx8mn-bsh-smm-s2-common.dtsi"
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/ {
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model = "BSH SMM S2 PRO";
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compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn";
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0x0 0x20000000>;
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};
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};
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/* eMMC */
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&iomuxc {
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090
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MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d0
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MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d0
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MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d0
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MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d0
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MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d0
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MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d0
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MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d0
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MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d0
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MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d0
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MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x090
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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fsl,pins = <
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MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094
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MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4
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MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d4
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MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d4
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MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d4
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MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d4
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MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d4
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MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d4
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MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d4
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MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d4
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MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x094
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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fsl,pins = <
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MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096
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MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6
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MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d6
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MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d6
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MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d6
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MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d6
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MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d6
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MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d6
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MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d6
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MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d6
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MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x096
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>;
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};
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};
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