mirror of
https://github.com/AsahiLinux/u-boot
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6d97dc10a8
To i.MX6SX/UL, two ethernet interfaces are supported. Add ENET2 clock support: 1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed. To value 1, only i.MX6SX/UL can pass the check. 2. Modify board code who use this api to follow new api prototype. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
915 lines
22 KiB
C
915 lines
22 KiB
C
/*
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* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <div64.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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enum pll_clocks {
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PLL_SYS, /* System PLL */
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PLL_BUS, /* System Bus PLL*/
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PLL_USBOTG, /* OTG USB PLL */
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PLL_ENET, /* ENET PLL */
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};
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struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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#ifdef CONFIG_MXC_OCOTP
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void enable_ocotp_clk(unsigned char enable)
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{
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u32 reg;
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reg = __raw_readl(&imx_ccm->CCGR2);
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if (enable)
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reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
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else
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reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
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__raw_writel(reg, &imx_ccm->CCGR2);
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}
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#endif
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#ifdef CONFIG_NAND_MXS
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void setup_gpmi_io_clk(u32 cfg)
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{
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/* Disable clocks per ERR007177 from MX6 errata */
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clrbits_le32(&imx_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
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clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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clrsetbits_le32(&imx_ccm->cs2cdr,
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MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
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MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
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cfg);
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setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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setbits_le32(&imx_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
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}
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#endif
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void enable_usboh3_clk(unsigned char enable)
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{
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u32 reg;
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reg = __raw_readl(&imx_ccm->CCGR6);
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if (enable)
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reg |= MXC_CCM_CCGR6_USBOH3_MASK;
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else
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reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
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__raw_writel(reg, &imx_ccm->CCGR6);
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}
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#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
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void enable_enet_clk(unsigned char enable)
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{
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u32 mask, *addr;
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if (is_cpu_type(MXC_CPU_MX6UL)) {
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mask = MXC_CCM_CCGR3_ENET_MASK;
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addr = &imx_ccm->CCGR3;
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} else {
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mask = MXC_CCM_CCGR1_ENET_MASK;
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addr = &imx_ccm->CCGR1;
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}
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if (enable)
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setbits_le32(addr, mask);
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else
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clrbits_le32(addr, mask);
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}
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#endif
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#ifdef CONFIG_MXC_UART
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void enable_uart_clk(unsigned char enable)
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{
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u32 mask;
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if (is_cpu_type(MXC_CPU_MX6UL))
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mask = MXC_CCM_CCGR5_UART_MASK;
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else
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mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
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if (enable)
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setbits_le32(&imx_ccm->CCGR5, mask);
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else
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clrbits_le32(&imx_ccm->CCGR5, mask);
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}
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#endif
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#ifdef CONFIG_MMC
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int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
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{
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u32 mask;
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if (bus_num > 3)
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return -EINVAL;
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mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
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if (enable)
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setbits_le32(&imx_ccm->CCGR6, mask);
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else
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clrbits_le32(&imx_ccm->CCGR6, mask);
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return 0;
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}
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#endif
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#ifdef CONFIG_SYS_I2C_MXC
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/* i2c_num can be from 0 - 3 */
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
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{
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u32 reg;
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u32 mask;
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u32 *addr;
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if (i2c_num > 3)
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return -EINVAL;
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if (i2c_num < 3) {
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mask = MXC_CCM_CCGR_CG_MASK
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<< (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
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+ (i2c_num << 1));
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reg = __raw_readl(&imx_ccm->CCGR2);
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if (enable)
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reg |= mask;
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else
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reg &= ~mask;
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__raw_writel(reg, &imx_ccm->CCGR2);
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} else {
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if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
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mask = MXC_CCM_CCGR6_I2C4_MASK;
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addr = &imx_ccm->CCGR6;
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} else {
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mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
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addr = &imx_ccm->CCGR1;
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}
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reg = __raw_readl(addr);
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if (enable)
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reg |= mask;
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else
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reg &= ~mask;
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__raw_writel(reg, addr);
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}
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return 0;
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}
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#endif
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/* spi_num can be from 0 - SPI_MAX_NUM */
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int enable_spi_clk(unsigned char enable, unsigned spi_num)
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{
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u32 reg;
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u32 mask;
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if (spi_num > SPI_MAX_NUM)
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return -EINVAL;
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mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
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reg = __raw_readl(&imx_ccm->CCGR1);
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if (enable)
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reg |= mask;
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else
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reg &= ~mask;
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__raw_writel(reg, &imx_ccm->CCGR1);
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return 0;
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}
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static u32 decode_pll(enum pll_clocks pll, u32 infreq)
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{
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u32 div;
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switch (pll) {
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case PLL_SYS:
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div = __raw_readl(&imx_ccm->analog_pll_sys);
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div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
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return (infreq * div) >> 1;
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case PLL_BUS:
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div = __raw_readl(&imx_ccm->analog_pll_528);
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div &= BM_ANADIG_PLL_528_DIV_SELECT;
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return infreq * (20 + (div << 1));
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case PLL_USBOTG:
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div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
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div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
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return infreq * (20 + (div << 1));
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case PLL_ENET:
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div = __raw_readl(&imx_ccm->analog_pll_enet);
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div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
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return 25000000 * (div + (div >> 1) + 1);
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default:
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return 0;
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}
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/* NOTREACHED */
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}
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static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
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{
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u32 div;
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u64 freq;
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switch (pll) {
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case PLL_BUS:
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if (!is_cpu_type(MXC_CPU_MX6UL)) {
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if (pfd_num == 3) {
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/* No PFD3 on PPL2 */
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return 0;
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}
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}
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div = __raw_readl(&imx_ccm->analog_pfd_528);
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freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
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break;
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case PLL_USBOTG:
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div = __raw_readl(&imx_ccm->analog_pfd_480);
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freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
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break;
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default:
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/* No PFD on other PLL */
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return 0;
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}
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return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
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ANATOP_PFD_FRAC_SHIFT(pfd_num));
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}
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static u32 get_mcu_main_clk(void)
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{
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u32 reg, freq;
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reg = __raw_readl(&imx_ccm->cacrr);
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reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
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reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
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freq = decode_pll(PLL_SYS, MXC_HCLK);
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return freq / (reg + 1);
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}
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u32 get_periph_clk(void)
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{
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u32 reg, div = 0, freq = 0;
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reg = __raw_readl(&imx_ccm->cbcdr);
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if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
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div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
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MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
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reg = __raw_readl(&imx_ccm->cbcmr);
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reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
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reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
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switch (reg) {
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case 0:
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freq = decode_pll(PLL_USBOTG, MXC_HCLK);
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break;
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case 1:
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case 2:
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freq = MXC_HCLK;
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break;
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default:
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break;
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}
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} else {
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reg = __raw_readl(&imx_ccm->cbcmr);
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reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
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reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
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switch (reg) {
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case 0:
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freq = decode_pll(PLL_BUS, MXC_HCLK);
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break;
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case 1:
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freq = mxc_get_pll_pfd(PLL_BUS, 2);
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break;
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case 2:
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freq = mxc_get_pll_pfd(PLL_BUS, 0);
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break;
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case 3:
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/* static / 2 divider */
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freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
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break;
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default:
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break;
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}
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}
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return freq / (div + 1);
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}
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static u32 get_ipg_clk(void)
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{
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u32 reg, ipg_podf;
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reg = __raw_readl(&imx_ccm->cbcdr);
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reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
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ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
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return get_ahb_clk() / (ipg_podf + 1);
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}
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static u32 get_ipg_per_clk(void)
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{
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u32 reg, perclk_podf;
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reg = __raw_readl(&imx_ccm->cscmr1);
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if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
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is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
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if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
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return MXC_HCLK; /* OSC 24Mhz */
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}
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perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
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return get_ipg_clk() / (perclk_podf + 1);
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}
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static u32 get_uart_clk(void)
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{
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u32 reg, uart_podf;
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u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
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reg = __raw_readl(&imx_ccm->cscdr1);
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if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
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is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
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if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
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freq = MXC_HCLK;
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}
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reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
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uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
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return freq / (uart_podf + 1);
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}
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static u32 get_cspi_clk(void)
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{
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u32 reg, cspi_podf;
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reg = __raw_readl(&imx_ccm->cscdr2);
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cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
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MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
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if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
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is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
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if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
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return MXC_HCLK / (cspi_podf + 1);
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}
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return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
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}
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static u32 get_axi_clk(void)
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{
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u32 root_freq, axi_podf;
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u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
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axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
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axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
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if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
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if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
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root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
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else
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root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
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} else
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root_freq = get_periph_clk();
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return root_freq / (axi_podf + 1);
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}
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static u32 get_emi_slow_clk(void)
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{
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u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
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cscmr1 = __raw_readl(&imx_ccm->cscmr1);
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emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
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emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
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emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
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emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
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switch (emi_clk_sel) {
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case 0:
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root_freq = get_axi_clk();
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break;
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case 1:
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root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
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break;
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case 2:
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root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
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break;
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case 3:
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root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
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break;
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}
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return root_freq / (emi_slow_podf + 1);
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}
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static u32 get_mmdc_ch0_clk(void)
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{
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u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
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u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
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u32 freq, podf, per2_clk2_podf;
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if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
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is_cpu_type(MXC_CPU_MX6SL)) {
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podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
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MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
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if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
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per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
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MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
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if (is_cpu_type(MXC_CPU_MX6SL)) {
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if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
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freq = MXC_HCLK;
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else
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freq = decode_pll(PLL_USBOTG, MXC_HCLK);
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} else {
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if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
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freq = decode_pll(PLL_BUS, MXC_HCLK);
|
|
else
|
|
freq = decode_pll(PLL_USBOTG, MXC_HCLK);
|
|
}
|
|
} else {
|
|
per2_clk2_podf = 0;
|
|
switch ((cbcmr &
|
|
MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
|
|
MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
|
|
case 0:
|
|
freq = decode_pll(PLL_BUS, MXC_HCLK);
|
|
break;
|
|
case 1:
|
|
freq = mxc_get_pll_pfd(PLL_BUS, 2);
|
|
break;
|
|
case 2:
|
|
freq = mxc_get_pll_pfd(PLL_BUS, 0);
|
|
break;
|
|
case 3:
|
|
/* static / 2 divider */
|
|
freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
|
|
break;
|
|
}
|
|
}
|
|
return freq / (podf + 1) / (per2_clk2_podf + 1);
|
|
} else {
|
|
podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
|
|
MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
|
|
return get_periph_clk() / (podf + 1);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_FSL_QSPI
|
|
/* qspi_num can be from 0 - 1 */
|
|
void enable_qspi_clk(int qspi_num)
|
|
{
|
|
u32 reg = 0;
|
|
/* Enable QuadSPI clock */
|
|
switch (qspi_num) {
|
|
case 0:
|
|
/* disable the clock gate */
|
|
clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
|
|
|
|
/* set 50M : (50 = 396 / 2 / 4) */
|
|
reg = readl(&imx_ccm->cscmr1);
|
|
reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
|
|
MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
|
|
reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
|
|
(2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
|
|
writel(reg, &imx_ccm->cscmr1);
|
|
|
|
/* enable the clock gate */
|
|
setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
|
|
break;
|
|
case 1:
|
|
/*
|
|
* disable the clock gate
|
|
* QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
|
|
* disable both of them.
|
|
*/
|
|
clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
|
|
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
|
|
|
|
/* set 50M : (50 = 396 / 2 / 4) */
|
|
reg = readl(&imx_ccm->cs2cdr);
|
|
reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
|
|
MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
|
|
MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
|
|
reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
|
|
MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
|
|
writel(reg, &imx_ccm->cs2cdr);
|
|
|
|
/*enable the clock gate*/
|
|
setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
|
|
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_FEC_MXC
|
|
int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
|
|
{
|
|
u32 reg = 0;
|
|
s32 timeout = 100000;
|
|
|
|
struct anatop_regs __iomem *anatop =
|
|
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
|
|
|
|
if (freq < ENET_25MHZ || freq > ENET_125MHZ)
|
|
return -EINVAL;
|
|
|
|
if (fec_id == 0) {
|
|
reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
|
|
reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
|
|
} else if (fec_id == 1) {
|
|
/* Only i.MX6SX/UL support ENET2 */
|
|
if (!(is_cpu_type(MXC_CPU_MX6SX) ||
|
|
is_cpu_type(MXC_CPU_MX6UL)))
|
|
return -EINVAL;
|
|
reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
|
|
reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
|
|
} else {
|
|
return -EINVAL;
|
|
}
|
|
|
|
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
|
|
(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
|
|
reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
|
|
writel(reg, &anatop->pll_enet);
|
|
while (timeout--) {
|
|
if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
|
|
break;
|
|
}
|
|
if (timeout < 0)
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
/* Enable FEC clock */
|
|
if (fec_id == 0)
|
|
reg |= BM_ANADIG_PLL_ENET_ENABLE;
|
|
else
|
|
reg |= BM_ANADIG_PLL_ENET2_ENABLE;
|
|
reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
|
|
writel(reg, &anatop->pll_enet);
|
|
|
|
#ifdef CONFIG_MX6SX
|
|
/*
|
|
* Set enet ahb clock to 200MHz
|
|
* pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
|
|
*/
|
|
reg = readl(&imx_ccm->chsccdr);
|
|
reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
|
|
| MXC_CCM_CHSCCDR_ENET_PODF_MASK
|
|
| MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
|
|
/* PLL2 PFD2 */
|
|
reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
|
|
/* Div = 2*/
|
|
reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
|
|
reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
|
|
writel(reg, &imx_ccm->chsccdr);
|
|
|
|
/* Enable enet system clock */
|
|
reg = readl(&imx_ccm->CCGR3);
|
|
reg |= MXC_CCM_CCGR3_ENET_MASK;
|
|
writel(reg, &imx_ccm->CCGR3);
|
|
#endif
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static u32 get_usdhc_clk(u32 port)
|
|
{
|
|
u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
|
|
u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
|
|
u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
|
|
|
|
switch (port) {
|
|
case 0:
|
|
usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
|
|
MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
|
|
clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
|
|
|
|
break;
|
|
case 1:
|
|
usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
|
|
MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
|
|
clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
|
|
|
|
break;
|
|
case 2:
|
|
usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
|
|
MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
|
|
clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
|
|
|
|
break;
|
|
case 3:
|
|
usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
|
|
MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
|
|
clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
|
|
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (clk_sel)
|
|
root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
|
|
else
|
|
root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
|
|
|
|
return root_freq / (usdhc_podf + 1);
|
|
}
|
|
|
|
u32 imx_get_uartclk(void)
|
|
{
|
|
return get_uart_clk();
|
|
}
|
|
|
|
u32 imx_get_fecclk(void)
|
|
{
|
|
return mxc_get_clock(MXC_IPG_CLK);
|
|
}
|
|
|
|
#if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
|
|
static int enable_enet_pll(uint32_t en)
|
|
{
|
|
struct mxc_ccm_reg *const imx_ccm
|
|
= (struct mxc_ccm_reg *) CCM_BASE_ADDR;
|
|
s32 timeout = 100000;
|
|
u32 reg = 0;
|
|
|
|
/* Enable PLLs */
|
|
reg = readl(&imx_ccm->analog_pll_enet);
|
|
reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
|
|
writel(reg, &imx_ccm->analog_pll_enet);
|
|
reg |= BM_ANADIG_PLL_SYS_ENABLE;
|
|
while (timeout--) {
|
|
if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
|
|
break;
|
|
}
|
|
if (timeout <= 0)
|
|
return -EIO;
|
|
reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
|
|
writel(reg, &imx_ccm->analog_pll_enet);
|
|
reg |= en;
|
|
writel(reg, &imx_ccm->analog_pll_enet);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CMD_SATA
|
|
static void ungate_sata_clock(void)
|
|
{
|
|
struct mxc_ccm_reg *const imx_ccm =
|
|
(struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
/* Enable SATA clock. */
|
|
setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
|
|
}
|
|
|
|
int enable_sata_clock(void)
|
|
{
|
|
ungate_sata_clock();
|
|
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
|
|
}
|
|
|
|
void disable_sata_clock(void)
|
|
{
|
|
struct mxc_ccm_reg *const imx_ccm =
|
|
(struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE_IMX
|
|
static void ungate_pcie_clock(void)
|
|
{
|
|
struct mxc_ccm_reg *const imx_ccm =
|
|
(struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
/* Enable PCIe clock. */
|
|
setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
|
|
}
|
|
|
|
int enable_pcie_clock(void)
|
|
{
|
|
struct anatop_regs *anatop_regs =
|
|
(struct anatop_regs *)ANATOP_BASE_ADDR;
|
|
struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
u32 lvds1_clk_sel;
|
|
|
|
/*
|
|
* Here be dragons!
|
|
*
|
|
* The register ANATOP_MISC1 is not documented in the Freescale
|
|
* MX6RM. The register that is mapped in the ANATOP space and
|
|
* marked as ANATOP_MISC1 is actually documented in the PMU section
|
|
* of the datasheet as PMU_MISC1.
|
|
*
|
|
* Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
|
|
* mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
|
|
* for PCI express link that is clocked from the i.MX6.
|
|
*/
|
|
#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
|
|
#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
|
|
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
|
|
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
|
|
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
|
|
|
|
if (is_cpu_type(MXC_CPU_MX6SX))
|
|
lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
|
|
else
|
|
lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
|
|
|
|
clrsetbits_le32(&anatop_regs->ana_misc1,
|
|
ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
|
|
ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
|
|
ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
|
|
|
|
/* PCIe reference clock sourced from AXI. */
|
|
clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
|
|
|
|
/* Party time! Ungate the clock to the PCIe. */
|
|
#ifdef CONFIG_CMD_SATA
|
|
ungate_sata_clock();
|
|
#endif
|
|
ungate_pcie_clock();
|
|
|
|
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
|
|
BM_ANADIG_PLL_ENET_ENABLE_PCIE);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SECURE_BOOT
|
|
void hab_caam_clock_enable(unsigned char enable)
|
|
{
|
|
u32 reg;
|
|
|
|
/* CG4 ~ CG6, CAAM clocks */
|
|
reg = __raw_readl(&imx_ccm->CCGR0);
|
|
if (enable)
|
|
reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
|
|
MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
|
|
MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
|
|
else
|
|
reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
|
|
MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
|
|
MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
|
|
__raw_writel(reg, &imx_ccm->CCGR0);
|
|
|
|
/* EMI slow clk */
|
|
reg = __raw_readl(&imx_ccm->CCGR6);
|
|
if (enable)
|
|
reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
|
|
else
|
|
reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
|
|
__raw_writel(reg, &imx_ccm->CCGR6);
|
|
}
|
|
#endif
|
|
|
|
static void enable_pll3(void)
|
|
{
|
|
struct anatop_regs __iomem *anatop =
|
|
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
|
|
|
|
/* make sure pll3 is enabled */
|
|
if ((readl(&anatop->usb1_pll_480_ctrl) &
|
|
BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
|
|
/* enable pll's power */
|
|
writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
|
|
&anatop->usb1_pll_480_ctrl_set);
|
|
writel(0x80, &anatop->ana_misc2_clr);
|
|
/* wait for pll lock */
|
|
while ((readl(&anatop->usb1_pll_480_ctrl) &
|
|
BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
|
|
;
|
|
/* disable bypass */
|
|
writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
|
|
&anatop->usb1_pll_480_ctrl_clr);
|
|
/* enable pll output */
|
|
writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
|
|
&anatop->usb1_pll_480_ctrl_set);
|
|
}
|
|
}
|
|
|
|
void enable_thermal_clk(void)
|
|
{
|
|
enable_pll3();
|
|
}
|
|
|
|
unsigned int mxc_get_clock(enum mxc_clock clk)
|
|
{
|
|
switch (clk) {
|
|
case MXC_ARM_CLK:
|
|
return get_mcu_main_clk();
|
|
case MXC_PER_CLK:
|
|
return get_periph_clk();
|
|
case MXC_AHB_CLK:
|
|
return get_ahb_clk();
|
|
case MXC_IPG_CLK:
|
|
return get_ipg_clk();
|
|
case MXC_IPG_PERCLK:
|
|
case MXC_I2C_CLK:
|
|
return get_ipg_per_clk();
|
|
case MXC_UART_CLK:
|
|
return get_uart_clk();
|
|
case MXC_CSPI_CLK:
|
|
return get_cspi_clk();
|
|
case MXC_AXI_CLK:
|
|
return get_axi_clk();
|
|
case MXC_EMI_SLOW_CLK:
|
|
return get_emi_slow_clk();
|
|
case MXC_DDR_CLK:
|
|
return get_mmdc_ch0_clk();
|
|
case MXC_ESDHC_CLK:
|
|
return get_usdhc_clk(0);
|
|
case MXC_ESDHC2_CLK:
|
|
return get_usdhc_clk(1);
|
|
case MXC_ESDHC3_CLK:
|
|
return get_usdhc_clk(2);
|
|
case MXC_ESDHC4_CLK:
|
|
return get_usdhc_clk(3);
|
|
case MXC_SATA_CLK:
|
|
return get_ahb_clk();
|
|
default:
|
|
printf("Unsupported MXC CLK: %d\n", clk);
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Dump some core clockes.
|
|
*/
|
|
int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|
{
|
|
u32 freq;
|
|
freq = decode_pll(PLL_SYS, MXC_HCLK);
|
|
printf("PLL_SYS %8d MHz\n", freq / 1000000);
|
|
freq = decode_pll(PLL_BUS, MXC_HCLK);
|
|
printf("PLL_BUS %8d MHz\n", freq / 1000000);
|
|
freq = decode_pll(PLL_USBOTG, MXC_HCLK);
|
|
printf("PLL_OTG %8d MHz\n", freq / 1000000);
|
|
freq = decode_pll(PLL_ENET, MXC_HCLK);
|
|
printf("PLL_NET %8d MHz\n", freq / 1000000);
|
|
|
|
printf("\n");
|
|
printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
|
|
printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
|
|
#ifdef CONFIG_MXC_SPI
|
|
printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
|
|
#endif
|
|
printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
|
|
printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
|
|
printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
|
|
printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
|
|
printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
|
|
printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
|
|
printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
|
|
printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
|
|
printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifndef CONFIG_MX6SX
|
|
void enable_ipu_clock(void)
|
|
{
|
|
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
int reg;
|
|
reg = readl(&mxc_ccm->CCGR3);
|
|
reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
|
|
writel(reg, &mxc_ccm->CCGR3);
|
|
|
|
if (is_mx6dqp()) {
|
|
setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
|
|
setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
|
|
}
|
|
}
|
|
#endif
|
|
/***************************************************/
|
|
|
|
U_BOOT_CMD(
|
|
clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
|
|
"display clocks",
|
|
""
|
|
);
|