mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 10:18:38 +00:00
c1b8819680
Update the compatible string of L2 cache. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
327 lines
6.9 KiB
Text
327 lines
6.9 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/dts-v1/;
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#include "binman.dtsi"
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#include "ae350-u-boot.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "andestech,a25";
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model = "andestech,a25";
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aliases {
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uart0 = &serial0;
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spi0 = &spi;
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};
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chosen {
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bootargs = "console=ttyS0,38400n8 debug loglevel=7";
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stdout-path = "uart0:38400n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <60000000>;
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CPU0: cpu@0 {
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv32imafdc";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <32>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <32>;
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next-level-cache = <&L2>;
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CPU0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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reg = <1>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv32imafdc";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <32>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <32>;
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next-level-cache = <&L2>;
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CPU1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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reg = <2>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv32imafdc";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <32>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <32>;
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next-level-cache = <&L2>;
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CPU2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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reg = <3>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv32imafdc";
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riscv,priv-major = <1>;
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riscv,priv-minor = <10>;
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mmu-type = "riscv,sv32";
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clock-frequency = <60000000>;
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i-cache-size = <0x8000>;
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i-cache-line-size = <32>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <32>;
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next-level-cache = <&L2>;
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CPU3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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L2: l2-cache@e0500000 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x40000>;
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reg = <0xe0500000 0x40000>;
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andes,inst-prefetch = <3>;
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andes,data-prefetch = <3>;
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/* The value format is <XRAMOCTL XRAMICTL> */
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andes,tag-ram-ctl = <0 0>;
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andes,data-ram-ctl = <0 0>;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x40000000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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plic0: interrupt-controller@e4000000 {
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compatible = "riscv,plic0";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe4000000 0x2000000>;
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riscv,ndev=<71>;
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interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
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&CPU1_intc 11 &CPU1_intc 9
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&CPU2_intc 11 &CPU2_intc 9
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&CPU3_intc 11 &CPU3_intc 9>;
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};
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plicsw: interrupt-controller@e6400000 {
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compatible = "andestech,plicsw";
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0xe6400000 0x400000>;
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riscv,ndev=<2>;
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interrupts-extended = <&CPU0_intc 3
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&CPU1_intc 3
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&CPU2_intc 3
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&CPU3_intc 3>;
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};
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plmt0@e6000000 {
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compatible = "andestech,plmt0";
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interrupts-extended = <&CPU0_intc 7
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&CPU1_intc 7
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&CPU2_intc 7
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&CPU3_intc 7>;
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reg = <0xe6000000 0x100000>;
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};
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};
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spiclk: virt_100mhz {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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};
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timer0: timer@f0400000 {
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compatible = "andestech,atcpit100";
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reg = <0xf0400000 0x1000>;
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clock-frequency = <60000000>;
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interrupts = <3 4>;
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interrupt-parent = <&plic0>;
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};
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serial0: serial@f0300000 {
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compatible = "andestech,uart16550", "ns16550a";
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reg = <0xf0300000 0x1000>;
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interrupts = <9 4>;
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clock-frequency = <19660800>;
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reg-shift = <2>;
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reg-offset = <32>;
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no-loopback-test = <1>;
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interrupt-parent = <&plic0>;
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};
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mac0: mac@e0100000 {
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compatible = "andestech,atmac100";
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reg = <0xe0100000 0x1000>;
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interrupts = <19 4>;
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interrupt-parent = <&plic0>;
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};
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mmc0: mmc@f0e00000 {
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compatible = "andestech,atfsdc010";
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max-frequency = <100000000>;
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clock-freq-min-max = <400000 100000000>;
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fifo-depth = <0x10>;
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reg = <0xf0e00000 0x1000>;
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interrupts = <18 4>;
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cap-sd-highspeed;
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interrupt-parent = <&plic0>;
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};
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dma0: dma@f0c00000 {
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compatible = "andestech,atcdmac300";
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reg = <0xf0c00000 0x1000>;
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interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
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dma-channels = <8>;
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interrupt-parent = <&plic0>;
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};
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lcd0: lcd@e0200000 {
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compatible = "andestech,atflcdc100";
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reg = <0xe0200000 0x1000>;
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interrupts = <20 4>;
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interrupt-parent = <&plic0>;
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};
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smc0: smc@e0400000 {
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compatible = "andestech,atfsmc020";
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reg = <0xe0400000 0x1000>;
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};
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snd0: snd@f0d00000 {
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compatible = "andestech,atfac97";
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reg = <0xf0d00000 0x1000>;
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interrupts = <17 4>;
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interrupt-parent = <&plic0>;
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};
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pmu {
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compatible = "riscv,base-pmu";
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};
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virtio_mmio@fe007000 {
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interrupts = <0x17 0x4>;
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interrupt-parent = <0x2>;
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reg = <0xfe007000 0x1000>;
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compatible = "virtio,mmio";
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};
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virtio_mmio@fe006000 {
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interrupts = <0x16 0x4>;
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interrupt-parent = <0x2>;
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reg = <0xfe006000 0x1000>;
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compatible = "virtio,mmio";
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};
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virtio_mmio@fe005000 {
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interrupts = <0x15 0x4>;
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interrupt-parent = <0x2>;
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reg = <0xfe005000 0x1000>;
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compatible = "virtio,mmio";
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};
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virtio_mmio@fe004000 {
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interrupts = <0x14 0x4>;
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interrupt-parent = <0x2>;
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reg = <0xfe004000 0x1000>;
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compatible = "virtio,mmio";
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};
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virtio_mmio@fe003000 {
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interrupts = <0x13 0x4>;
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interrupt-parent = <0x2>;
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reg = <0xfe003000 0x1000>;
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compatible = "virtio,mmio";
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};
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virtio_mmio@fe002000 {
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interrupts = <0x12 0x4>;
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interrupt-parent = <0x2>;
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reg = <0xfe002000 0x1000>;
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compatible = "virtio,mmio";
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};
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virtio_mmio@fe001000 {
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interrupts = <0x11 0x4>;
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interrupt-parent = <0x2>;
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reg = <0xfe001000 0x1000>;
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compatible = "virtio,mmio";
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};
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virtio_mmio@fe000000 {
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interrupts = <0x10 0x4>;
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interrupt-parent = <0x2>;
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reg = <0xfe000000 0x1000>;
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compatible = "virtio,mmio";
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};
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x88000000 0x4000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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spi: spi@f0b00000 {
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compatible = "andestech,atcspi200";
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reg = <0xf0b00000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <1>;
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clocks = <&spiclk>;
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interrupts = <4 4>;
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interrupt-parent = <&plic0>;
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flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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spi-cpol;
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spi-cpha;
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};
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};
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};
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