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730a402450
Add the clock driver for the rk3066 platform. Derived from the rk3288 and rk3188 driver it supports only a bare minimum to bring up the system to reduce the TPL size for: SDRAM clock configuration. The boot devices NAND, EMMC, SDMMC, SPI. A UART for the debug messages (fixed) at 115200n8. A SARADC for the recovery button. A TIMER for the delays (fixed). There's support for two possible frequencies, the safe 600MHz which will work with default pmic settings and will be set to get away from the 24MHz default and the maximum of 1.416Ghz, which boards can set if they were able to get pmic support for it. After the clock tree is set during the TPL probe there's no parent update support. In OF_REAL mode the drivers ns16550.c and dw-apb-timer.c obtain the (fixed) clk_get_rate from the clock driver instead of platdata. The rk3066 cru node has a number of assigned-clocks properties that call the .set_rate() function. Add them to the list so that they return a 0 instead of -ENOENT. Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> |
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|---|---|---|
| .. | ||
| clk_pll.c | ||
| clk_px30.c | ||
| clk_rk322x.c | ||
| clk_rk3036.c | ||
| clk_rk3066.c | ||
| clk_rk3128.c | ||
| clk_rk3188.c | ||
| clk_rk3288.c | ||
| clk_rk3308.c | ||
| clk_rk3328.c | ||
| clk_rk3368.c | ||
| clk_rk3399.c | ||
| clk_rk3568.c | ||
| clk_rv1108.c | ||
| Makefile | ||