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The available defconfigs for RISC-V QEMU have changed. We now have configurations to compile U-Boot to run in supervisor mode and for U-Boot SPL. Update the QEMU RISC-V documentation to reflect these changes. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> |
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| AndesTech | ||
| atmel | ||
| coreboot | ||
| emulation | ||
| freescale | ||
| intel | ||
| renesas | ||
| sifive | ||
| xilinx | ||
| index.rst | ||