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cfe673cda7
Add support for the suniv architecture, which is newer ARM9 SoCs by Allwinner. The design of it seems to be a mixture of sun3i, sun4i and sun6i. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
377 lines
10 KiB
C
377 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* sun6i specific clock code
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*
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* (C) Copyright 2007-2012
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/prcm.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#ifdef CONFIG_SPL_BUILD
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void clock_init_safe(void)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) && \
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!defined(CONFIG_MACH_SUNIV)
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struct sunxi_prcm_reg * const prcm =
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(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
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/* Set PLL ldo voltage without this PLL6 does not work properly */
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clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
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PRCM_PLL_CTRL_LDO_KEY);
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clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
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PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
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PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
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clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
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#endif
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#if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
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/* Set PLL lock enable bits and switch to old lock mode */
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writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);
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#endif
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clock_set_pll1(408000000);
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writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
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while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
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;
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writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
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if (!IS_ENABLED(CONFIG_MACH_SUNIV)) {
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writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
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if (IS_ENABLED(CONFIG_MACH_SUN6I))
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writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
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}
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#if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
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setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
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setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA);
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setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
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setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE);
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#endif
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}
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#endif
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void clock_init_sec(void)
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{
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#ifdef CONFIG_MACH_SUNXI_H3_H5
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_prcm_reg * const prcm =
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(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
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setbits_le32(&ccm->ccu_sec_switch,
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CCM_SEC_SWITCH_MBUS_NONSEC |
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CCM_SEC_SWITCH_BUS_NONSEC |
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CCM_SEC_SWITCH_PLL_NONSEC);
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setbits_le32(&prcm->prcm_sec_switch,
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PRCM_SEC_SWITCH_APB0_CLK_NONSEC |
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PRCM_SEC_SWITCH_PLL_CFG_NONSEC |
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PRCM_SEC_SWITCH_PWR_GATE_NONSEC);
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#endif
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}
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void clock_init_uart(void)
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{
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#if CONFIG_CONS_INDEX < 5
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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#ifdef CONFIG_MACH_SUNIV
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/* suniv doesn't have apb2, UART clock source is always apb1 */
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/* open the clock for uart */
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setbits_le32(&ccm->apb1_gate,
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CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
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CONFIG_CONS_INDEX - 1));
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/* deassert uart reset */
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setbits_le32(&ccm->apb1_reset_cfg,
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1 << (APB1_RESET_UART_SHIFT +
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CONFIG_CONS_INDEX - 1));
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#else
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/* uart clock source is apb2 */
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writel(APB2_CLK_SRC_OSC24M|
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APB2_CLK_RATE_N_1|
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APB2_CLK_RATE_M(1),
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&ccm->apb2_div);
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/* open the clock for uart */
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setbits_le32(&ccm->apb2_gate,
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CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
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CONFIG_CONS_INDEX - 1));
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/* deassert uart reset */
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setbits_le32(&ccm->apb2_reset_cfg,
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1 << (APB2_RESET_UART_SHIFT +
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CONFIG_CONS_INDEX - 1));
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#endif /* !CONFIG_MACH_SUNIV */
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#else /* CONFIG_CONS_INDEX >= 5 */
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/* enable R_PIO and R_UART clocks, and de-assert resets */
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prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
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#endif
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}
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#ifdef CONFIG_SPL_BUILD
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void clock_set_pll1(unsigned int clk)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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const int p = 0;
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int k = 1;
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int m = 1;
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if (clk > 1152000000) {
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k = 2;
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} else if (clk > 768000000) {
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k = 4;
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m = 2;
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}
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/* Switch to 24MHz clock while changing PLL1 */
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if (IS_ENABLED(CONFIG_MACH_SUNIV)) {
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writel(CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
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&ccm->cpu_axi_cfg);
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} else {
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writel(AXI_DIV_3 << AXI_DIV_SHIFT |
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ATB_DIV_2 << ATB_DIV_SHIFT |
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CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
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&ccm->cpu_axi_cfg);
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}
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/*
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* sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
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* sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
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*/
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writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
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CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
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CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
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sdelay(200);
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/* Switch CPU to PLL1 */
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if (IS_ENABLED(CONFIG_MACH_SUNIV)) {
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writel(CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
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&ccm->cpu_axi_cfg);
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} else {
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writel(AXI_DIV_3 << AXI_DIV_SHIFT |
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ATB_DIV_2 << ATB_DIV_SHIFT |
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CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
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&ccm->cpu_axi_cfg);
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}
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}
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#endif
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void clock_set_pll3(unsigned int clk)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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#ifdef CONFIG_SUNXI_DE2
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const int m = 4; /* 6 MHz steps to allow higher frequency for DE2 */
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#else
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const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
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#endif
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if (clk == 0) {
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clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
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return;
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}
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/* PLL3 rate = 24000000 * n / m */
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writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
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CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
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&ccm->pll3_cfg);
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}
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#ifdef CONFIG_SUNXI_DE2
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void clock_set_pll3_factors(int m, int n)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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/* PLL3 rate = 24000000 * n / m */
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writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
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CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m),
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&ccm->pll3_cfg);
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while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK))
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;
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}
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#endif
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void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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const int max_n = 32;
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int k = 1, m = 2;
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#ifdef CONFIG_MACH_SUNXI_H3_H5
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clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK |
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CCM_PLL5_TUN_INIT_FREQ_MASK,
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CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16));
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#endif
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if (sigma_delta_enable)
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writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
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/* PLL5 rate = 24000000 * n * k / m */
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if (clk > 24000000 * k * max_n / m) {
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m = 1;
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if (clk > 24000000 * k * max_n / m)
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k = 2;
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}
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writel(CCM_PLL5_CTRL_EN |
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(sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
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CCM_PLL5_CTRL_UPD |
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CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
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CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
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udelay(5500);
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}
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#ifdef CONFIG_MACH_SUN6I
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void clock_set_mipi_pll(unsigned int clk)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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unsigned int k, m, n, value, diff;
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unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
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unsigned int src = clock_get_pll3();
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/* All calculations are in KHz to avoid overflows */
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clk /= 1000;
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src /= 1000;
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/* Pick the closest lower clock */
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for (k = 1; k <= 4; k++) {
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for (m = 1; m <= 16; m++) {
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for (n = 1; n <= 16; n++) {
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value = src * n * k / m;
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if (value > clk)
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continue;
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diff = clk - value;
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if (diff < best_diff) {
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best_diff = diff;
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best_k = k;
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best_m = m;
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best_n = n;
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}
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if (diff == 0)
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goto done;
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}
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}
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}
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done:
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writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
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CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
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CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
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}
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#endif
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#ifdef CONFIG_SUNXI_DE2
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void clock_set_pll10(unsigned int clk)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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const int m = 2; /* 12 MHz steps */
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if (clk == 0) {
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clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN);
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return;
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}
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/* PLL10 rate = 24000000 * n / m */
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writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE |
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CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m),
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&ccm->pll10_cfg);
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while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK))
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;
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}
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#endif
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#if defined(CONFIG_MACH_SUN8I_A33) || \
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defined(CONFIG_MACH_SUN8I_R40) || \
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defined(CONFIG_MACH_SUN50I)
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void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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if (sigma_delta_enable)
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writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0);
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writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
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(sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
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CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
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while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
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;
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}
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#endif
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unsigned int clock_get_pll3(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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uint32_t rval = readl(&ccm->pll3_cfg);
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int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
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int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
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/* Multiply by 1000 after dividing by m to avoid integer overflows */
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return (24000 * n / m) * 1000;
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}
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unsigned int clock_get_pll6(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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uint32_t rval = readl(&ccm->pll6_cfg);
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int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
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int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
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if (IS_ENABLED(CONFIG_MACH_SUNIV))
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return 24000000 * n * k;
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else
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return 24000000 * n * k / 2;
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}
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unsigned int clock_get_mipi_pll(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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uint32_t rval = readl(&ccm->mipi_pll_cfg);
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unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
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unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
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unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
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unsigned int src = clock_get_pll3();
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/* Multiply by 1000 after dividing by m to avoid integer overflows */
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return ((src / 1000) * n * k / m) * 1000;
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}
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void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
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{
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int pll = clock_get_pll6() * 2;
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int div = 1;
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while ((pll / div) > hz)
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div++;
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writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
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clk_cfg);
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}
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