mirror of
https://github.com/AsahiLinux/u-boot
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2a7232371a
The commit
642b80d256 ("net: designware: drop compatible altr, socfpga-stmmac")
breaks designware ethernet for all ARC boards. It removes
"altr, socfpga-stmmac" compatible from "drivers/net/designware.c"
without changing compatible in the boards which use it.
Fix that by adding "snps,arc-dwmac-3.70a" compatible string to
"drivers/net/designware.c" and using it in ARC boards device tree.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
144 lines
3.6 KiB
Text
144 lines
3.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Synopsys, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include "skeleton.dtsi"
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#include "dt-bindings/clock/snps,hsdk-cgu.h"
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/ {
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model = "snps,hsdk";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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console = &uart0;
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spi0 = &spi0;
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};
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cpu_card {
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core_clk: core_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <500000000>;
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u-boot,dm-pre-reloc;
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};
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};
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clk-fmeas {
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clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
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<&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
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<&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
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<&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
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<&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
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<&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
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<&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
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<&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
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<&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
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<&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
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<&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
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<&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
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<&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
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clock-names = "cpu-pll", "sys-pll",
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"tun-pll", "ddr-clk",
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"cpu-clk", "hdmi-pll",
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"tun-clk", "hdmi-clk",
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"apb-clk", "axi-clk",
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"eth-clk", "usb-clk",
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"sdio-clk", "hdmi-sys-clk",
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"gfx-core-clk", "gfx-dma-clk",
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"gfx-cfg-clk", "dmac-core-clk",
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"dmac-cfg-clk", "sdio-ref-clk",
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"spi-clk", "i2c-clk",
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"uart-clk", "ebi-clk",
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"rom-clk", "pwm-clk";
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};
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cgu_clk: cgu-clk@f0000000 {
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compatible = "snps,hsdk-cgu-clock";
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reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
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#clock-cells = <1>;
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};
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uart0: serial0@f0005000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xf0005000 0x1000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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ethernet@f0008000 {
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#interrupt-cells = <1>;
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compatible = "snps,arc-dwmac-3.70a";
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reg = <0xf0008000 0x2000>;
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phy-mode = "gmii";
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};
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ehci@0xf0040000 {
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compatible = "generic-ehci";
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reg = <0xf0040000 0x100>;
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};
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ohci@0xf0060000 {
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compatible = "generic-ohci";
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reg = <0xf0060000 0x100>;
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};
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mmcclk_ciu: mmcclk-ciu {
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compatible = "fixed-clock";
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/*
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* DW sdio controller has external ciu clock divider
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* controlled via register in SDIO IP. Due to its
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* unexpected default value (it should divide by 1
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* but it divides by 8) SDIO IP uses wrong clock and
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* works unstable (see STAR 9001204800)
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* We switched to the minimum possible value of the
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* divisor (div-by-2) in HSDK platform code.
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* So default mmcclk ciu clock is 50000000 Hz.
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*/
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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mmc: mmc0@f000a000 {
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compatible = "snps,dw-mshc";
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reg = <0xf000a000 0x400>;
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bus-width = <4>;
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fifo-depth = <256>;
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clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>;
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clock-names = "biu", "ciu";
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max-frequency = <25000000>;
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};
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spi0: spi@f0020000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0xf0020000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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spi-max-frequency = <4000000>;
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clocks = <&cgu_clk CLK_SYS_SPI_REF>;
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clock-names = "spi_clk";
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cs-gpio = <&cs_gpio 0>;
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spi_flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <4000000>;
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};
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};
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cs_gpio: gpio@f00014b0 {
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compatible = "snps,creg-gpio";
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reg = <0xf00014b0 0x4>;
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gpio-controller;
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#gpio-cells = <1>;
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gpio-bank-name = "hsdk-spi-cs";
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gpio-count = <1>;
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gpio-first-shift = <0>;
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gpio-bit-per-line = <2>;
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gpio-activate-val = <2>;
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gpio-deactivate-val = <3>;
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gpio-default-val = <1>;
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};
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};
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