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https://github.com/AsahiLinux/u-boot
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5e8317a9fa
clk_composite_ops was shared between all devices in the composite clock driver. If one clock had a feature (such as supporting set_parent) which another clock did not, it could call a null pointer dereference. This patch does three things 1. It adds null-pointer checks to all composite clock functions. 2. It makes clk_composite_ops const and sets its functions at compile-time. 3. It adds some basic sanity checks to num_parents. The combined effect of these changes is that any of mux, rate, or gate can be NULL, and composite clocks will still function normally. Previously, at least mux had to exist, since clk_composite_get_parent was used to determine the parent for clk_register. Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Lukasz Majewski <lukma@denx.de>
182 lines
4.3 KiB
C
182 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <clk-uclass.h>
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#include <dm/device.h>
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#include <dm/devres.h>
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#include <linux/clk-provider.h>
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#include <clk.h>
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#include <linux/err.h>
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#include "clk.h"
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#define UBOOT_DM_CLK_COMPOSITE "clk_composite"
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static u8 clk_composite_get_parent(struct clk *clk)
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{
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struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
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(struct clk *)dev_get_clk_ptr(clk->dev) : clk);
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struct clk *mux = composite->mux;
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if (mux)
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return clk_mux_get_parent(mux);
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else
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return 0;
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}
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static int clk_composite_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
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(struct clk *)dev_get_clk_ptr(clk->dev) : clk);
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const struct clk_ops *mux_ops = composite->mux_ops;
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struct clk *mux = composite->mux;
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if (mux && mux_ops)
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return mux_ops->set_parent(mux, parent);
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else
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return -ENOTSUPP;
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}
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static unsigned long clk_composite_recalc_rate(struct clk *clk)
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{
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struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
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(struct clk *)dev_get_clk_ptr(clk->dev) : clk);
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const struct clk_ops *rate_ops = composite->rate_ops;
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struct clk *rate = composite->rate;
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if (rate && rate_ops)
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return rate_ops->get_rate(rate);
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else
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return clk_get_parent_rate(clk);
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}
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static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
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{
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struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
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(struct clk *)dev_get_clk_ptr(clk->dev) : clk);
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const struct clk_ops *rate_ops = composite->rate_ops;
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struct clk *clk_rate = composite->rate;
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if (rate && rate_ops)
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return rate_ops->set_rate(clk_rate, rate);
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else
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return clk_get_rate(clk);
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}
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static int clk_composite_enable(struct clk *clk)
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{
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struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
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(struct clk *)dev_get_clk_ptr(clk->dev) : clk);
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const struct clk_ops *gate_ops = composite->gate_ops;
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struct clk *gate = composite->gate;
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if (gate && gate_ops)
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return gate_ops->enable(gate);
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else
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return 0;
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}
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static int clk_composite_disable(struct clk *clk)
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{
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struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
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(struct clk *)dev_get_clk_ptr(clk->dev) : clk);
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const struct clk_ops *gate_ops = composite->gate_ops;
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struct clk *gate = composite->gate;
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if (gate && gate_ops)
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return gate_ops->disable(gate);
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else
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return 0;
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}
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struct clk *clk_register_composite(struct device *dev, const char *name,
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const char * const *parent_names,
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int num_parents, struct clk *mux,
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const struct clk_ops *mux_ops,
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struct clk *rate,
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const struct clk_ops *rate_ops,
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struct clk *gate,
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const struct clk_ops *gate_ops,
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unsigned long flags)
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{
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struct clk *clk;
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struct clk_composite *composite;
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int ret;
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if (!num_parents || (num_parents != 1 && !mux))
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return ERR_PTR(-EINVAL);
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composite = kzalloc(sizeof(*composite), GFP_KERNEL);
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if (!composite)
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return ERR_PTR(-ENOMEM);
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if (mux && mux_ops) {
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composite->mux = mux;
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composite->mux_ops = mux_ops;
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mux->data = (ulong)composite;
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}
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if (rate && rate_ops) {
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if (!rate_ops->get_rate) {
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clk = ERR_PTR(-EINVAL);
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goto err;
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}
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composite->rate = rate;
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composite->rate_ops = rate_ops;
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rate->data = (ulong)composite;
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}
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if (gate && gate_ops) {
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if (!gate_ops->enable || !gate_ops->disable) {
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clk = ERR_PTR(-EINVAL);
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goto err;
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}
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composite->gate = gate;
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composite->gate_ops = gate_ops;
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gate->data = (ulong)composite;
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}
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clk = &composite->clk;
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ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, name,
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parent_names[clk_composite_get_parent(clk)]);
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if (ret) {
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clk = ERR_PTR(ret);
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goto err;
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}
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if (composite->mux)
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composite->mux->dev = clk->dev;
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if (composite->rate)
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composite->rate->dev = clk->dev;
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if (composite->gate)
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composite->gate->dev = clk->dev;
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return clk;
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err:
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kfree(composite);
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return clk;
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}
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static const struct clk_ops clk_composite_ops = {
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.set_parent = clk_composite_set_parent,
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.get_rate = clk_composite_recalc_rate,
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.set_rate = clk_composite_set_rate,
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.enable = clk_composite_enable,
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.disable = clk_composite_disable,
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};
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U_BOOT_DRIVER(clk_composite) = {
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.name = UBOOT_DM_CLK_COMPOSITE,
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.id = UCLASS_CLK,
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.ops = &clk_composite_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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