mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 02:08:38 +00:00
08f1d58aff
With all boards now using DM_ETH we determine the value for CONFIG_FEC_XCV_TYPE at run time, except in the case of the default fall-back. Set the fallback directly now. Cc: Fabio Estevam <festevam@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
127 lines
3.8 KiB
C
127 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2020 Toradex
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*/
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#ifndef __APALIS_IMX8X_H
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#define __APALIS_IMX8X_H
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#include <asm/arch/imx-regs.h>
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define USDHC1_BASE_ADDR 0x5b010000
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#define USDHC2_BASE_ADDR 0x5b020000
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#define CONFIG_IPADDR 192.168.10.2
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_SERVERIP 192.168.10.1
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#define MEM_LAYOUT_ENV_SETTINGS \
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"kernel_addr_r=0x80280000\0" \
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"fdt_addr_r=0x83100000\0" \
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"ramdisk_addr_r=0x8a000000\0" \
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"scriptaddr=0x83200000\0"
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#ifdef CONFIG_AHAB_BOOT
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#define AHAB_ENV "sec_boot=yes\0"
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#else
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#define AHAB_ENV "sec_boot=no\0"
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#endif
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/* Boot M4 */
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#define M4_BOOT_ENV \
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"m4_0_image=m4_0.bin\0" \
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"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
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"${m4_0_image}\0" \
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"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
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#define MFG_NAND_PARTITION ""
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#undef BOOTENV_RUN_NET_USB_START
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#define BOOTENV_RUN_NET_USB_START ""
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#define CONFIG_MFG_ENV_SETTINGS \
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"mfgtool_args=setenv bootargs ${consoleargs} " \
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"rdinit=/linuxrc g_mass_storage.stall=0 " \
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"g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \
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"g_mass_storage.idProduct=0x37FF " \
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"g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \
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"${vidargs} clk_ignore_unused\0" \
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"initrd_addr=0x83800000\0" \
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"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \
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"${fdt_addr};\0" \
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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AHAB_ENV \
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BOOTENV \
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CONFIG_MFG_ENV_SETTINGS \
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M4_BOOT_ENV \
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MEM_LAYOUT_ENV_SETTINGS \
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"boot_file=Image\0" \
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"consoleargs=console=ttyLP3,${baudrate} earlycon\0" \
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"fdt_file=imx8qxp-apalis-eval.dtb\0" \
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"fdtfile=imx8qxp-apalis-eval.dtb\0" \
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"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
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"image=Image\0" \
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"initrd_addr=0x83800000\0" \
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"mmcargs=setenv bootargs ${consoleargs} " \
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"root=PARTUUID=${uuid} rootwait " \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=1\0" \
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"netargs=setenv bootargs ${consoleargs} " \
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"root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
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"${vidargs}\0" \
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"nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \
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"apalis-imx8x/${fdt_file}; booti ${loadaddr} - " \
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"${fdt_addr}\0" \
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"panel=NULL\0" \
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"script=boot.scr\0" \
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"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
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"if test \"$confirm\" = \"y\"; then " \
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"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
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"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
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"${blkcnt}; fi\0" \
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"vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
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/* Environment in eMMC, before config block at the end of 1st "boot sector" */
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/* On Apalis iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define PHYS_SDRAM_1 0x80000000
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#define PHYS_SDRAM_2 0x880000000
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#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE SZ_2K
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 8000000 /* 8MHz */
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/* Networking */
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#define CONFIG_FEC_ENET_DEV 0
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#define IMX_FEC_BASE 0x5b040000
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#define CONFIG_FEC_MXC_PHYADDR 0x4
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#define PHY_ANEG_TIMEOUT 20000
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#endif /* __APALIS_IMX8X_H */
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