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79e5f27b09
The fec_halt() never free'd both RX and TX DMA descriptors that were allocated in fec_init(), nor did it free the RX buffers. Rework the FEC driver so that these descriptors and buffers are allocated only once in fec_probe(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
1098 lines
27 KiB
C
1098 lines
27 KiB
C
/*
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* (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
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* (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
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* (C) Copyright 2008 Armadeus Systems nc
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* (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <miiphy.h>
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#include "fec_mxc.h"
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <linux/compiler.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Timeout the transfer after 5 mS. This is usually a bit more, since
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* the code in the tightloops this timeout is used in adds some overhead.
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*/
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#define FEC_XFER_TIMEOUT 5000
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#ifndef CONFIG_MII
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#error "CONFIG_MII has to be defined!"
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#endif
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#ifndef CONFIG_FEC_XCV_TYPE
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#define CONFIG_FEC_XCV_TYPE MII100
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#endif
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/*
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* The i.MX28 operates with packets in big endian. We need to swap them before
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* sending and after receiving.
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*/
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#ifdef CONFIG_MX28
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#define CONFIG_FEC_MXC_SWAP_PACKET
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#endif
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#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
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/* Check various alignment issues at compile time */
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#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
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#error "ARCH_DMA_MINALIGN must be multiple of 16!"
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#endif
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#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
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(PKTALIGN % ARCH_DMA_MINALIGN != 0))
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#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
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#endif
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#undef DEBUG
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struct nbuf {
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uint8_t data[1500]; /**< actual data */
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int length; /**< actual length */
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int used; /**< buffer in use or not */
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uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
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};
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#ifdef CONFIG_FEC_MXC_SWAP_PACKET
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static void swap_packet(uint32_t *packet, int length)
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{
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int i;
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for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
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packet[i] = __swab32(packet[i]);
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}
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#endif
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/*
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* MII-interface related functions
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*/
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static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
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uint8_t regAddr)
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{
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uint32_t reg; /* convenient holder for the PHY register */
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uint32_t phy; /* convenient holder for the PHY */
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uint32_t start;
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int val;
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/*
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* reading from any PHY's register is done by properly
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* programming the FEC's MII data register.
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*/
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writel(FEC_IEVENT_MII, ð->ievent);
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reg = regAddr << FEC_MII_DATA_RA_SHIFT;
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phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
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writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
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phy | reg, ð->mii_data);
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/*
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* wait for the related interrupt
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*/
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start = get_timer(0);
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while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
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if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
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printf("Read MDIO failed...\n");
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return -1;
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}
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}
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/*
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* clear mii interrupt bit
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*/
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writel(FEC_IEVENT_MII, ð->ievent);
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/*
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* it's now safe to read the PHY's register
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*/
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val = (unsigned short)readl(ð->mii_data);
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debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
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regAddr, val);
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return val;
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}
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static void fec_mii_setspeed(struct ethernet_regs *eth)
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{
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/*
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* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
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* and do not drop the Preamble.
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*/
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writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
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ð->mii_speed);
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debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
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}
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static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
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uint8_t regAddr, uint16_t data)
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{
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uint32_t reg; /* convenient holder for the PHY register */
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uint32_t phy; /* convenient holder for the PHY */
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uint32_t start;
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reg = regAddr << FEC_MII_DATA_RA_SHIFT;
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phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
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writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
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FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
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/*
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* wait for the MII interrupt
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*/
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start = get_timer(0);
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while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
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if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
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printf("Write MDIO failed...\n");
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return -1;
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}
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}
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/*
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* clear MII interrupt bit
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*/
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writel(FEC_IEVENT_MII, ð->ievent);
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debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
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regAddr, data);
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return 0;
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}
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int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
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{
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return fec_mdio_read(bus->priv, phyAddr, regAddr);
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}
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int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
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u16 data)
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{
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return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
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}
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#ifndef CONFIG_PHYLIB
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static int miiphy_restart_aneg(struct eth_device *dev)
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{
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int ret = 0;
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#if !defined(CONFIG_FEC_MXC_NO_ANEG)
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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struct ethernet_regs *eth = fec->bus->priv;
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/*
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* Wake up from sleep if necessary
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* Reset PHY, then delay 300ns
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*/
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#ifdef CONFIG_MX27
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fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
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#endif
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fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
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udelay(1000);
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/*
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* Set the auto-negotiation advertisement register bits
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*/
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fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
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LPA_100FULL | LPA_100HALF | LPA_10FULL |
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LPA_10HALF | PHY_ANLPAR_PSB_802_3);
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fec_mdio_write(eth, fec->phy_id, MII_BMCR,
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BMCR_ANENABLE | BMCR_ANRESTART);
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if (fec->mii_postcall)
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ret = fec->mii_postcall(fec->phy_id);
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#endif
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return ret;
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}
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static int miiphy_wait_aneg(struct eth_device *dev)
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{
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uint32_t start;
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int status;
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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struct ethernet_regs *eth = fec->bus->priv;
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/*
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* Wait for AN completion
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*/
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start = get_timer(0);
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do {
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if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
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printf("%s: Autonegotiation timeout\n", dev->name);
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return -1;
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}
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status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
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if (status < 0) {
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printf("%s: Autonegotiation failed. status: %d\n",
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dev->name, status);
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return -1;
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}
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} while (!(status & BMSR_LSTATUS));
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return 0;
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}
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#endif
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static int fec_rx_task_enable(struct fec_priv *fec)
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{
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writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
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return 0;
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}
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static int fec_rx_task_disable(struct fec_priv *fec)
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{
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return 0;
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}
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static int fec_tx_task_enable(struct fec_priv *fec)
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{
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writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
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return 0;
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}
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static int fec_tx_task_disable(struct fec_priv *fec)
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{
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return 0;
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}
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/**
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* Initialize receive task's buffer descriptors
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* @param[in] fec all we know about the device yet
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* @param[in] count receive buffer count to be allocated
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* @param[in] dsize desired size of each receive buffer
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* @return 0 on success
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*
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* Init all RX descriptors to default values.
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*/
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static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
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{
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uint32_t size;
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uint8_t *data;
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int i;
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/*
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* Reload the RX descriptors with default values and wipe
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* the RX buffers.
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*/
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size = roundup(dsize, ARCH_DMA_MINALIGN);
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for (i = 0; i < count; i++) {
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data = (uint8_t *)fec->rbd_base[i].data_pointer;
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memset(data, 0, dsize);
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flush_dcache_range((uint32_t)data, (uint32_t)data + size);
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fec->rbd_base[i].status = FEC_RBD_EMPTY;
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fec->rbd_base[i].data_length = 0;
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}
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/* Mark the last RBD to close the ring. */
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fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
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fec->rbd_index = 0;
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flush_dcache_range((unsigned)fec->rbd_base,
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(unsigned)fec->rbd_base + size);
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}
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/**
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* Initialize transmit task's buffer descriptors
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* @param[in] fec all we know about the device yet
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*
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* Transmit buffers are created externally. We only have to init the BDs here.\n
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* Note: There is a race condition in the hardware. When only one BD is in
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* use it must be marked with the WRAP bit to use it for every transmitt.
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* This bit in combination with the READY bit results into double transmit
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* of each data buffer. It seems the state machine checks READY earlier then
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* resetting it after the first transfer.
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* Using two BDs solves this issue.
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*/
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static void fec_tbd_init(struct fec_priv *fec)
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{
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unsigned addr = (unsigned)fec->tbd_base;
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unsigned size = roundup(2 * sizeof(struct fec_bd),
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ARCH_DMA_MINALIGN);
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memset(fec->tbd_base, 0, size);
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fec->tbd_base[0].status = 0;
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fec->tbd_base[1].status = FEC_TBD_WRAP;
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fec->tbd_index = 0;
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flush_dcache_range(addr, addr + size);
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}
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/**
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* Mark the given read buffer descriptor as free
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* @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
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* @param[in] pRbd buffer descriptor to mark free again
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*/
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static void fec_rbd_clean(int last, struct fec_bd *pRbd)
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{
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unsigned short flags = FEC_RBD_EMPTY;
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if (last)
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flags |= FEC_RBD_WRAP;
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writew(flags, &pRbd->status);
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writew(0, &pRbd->data_length);
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}
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static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
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unsigned char *mac)
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{
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imx_get_mac_from_fuse(dev_id, mac);
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return !is_valid_ether_addr(mac);
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}
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static int fec_set_hwaddr(struct eth_device *dev)
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{
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uchar *mac = dev->enetaddr;
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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writel(0, &fec->eth->iaddr1);
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writel(0, &fec->eth->iaddr2);
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writel(0, &fec->eth->gaddr1);
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writel(0, &fec->eth->gaddr2);
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/*
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* Set physical address
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*/
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writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
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&fec->eth->paddr1);
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writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
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return 0;
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}
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/*
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* Do initial configuration of the FEC registers
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*/
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static void fec_reg_setup(struct fec_priv *fec)
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{
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uint32_t rcntrl;
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/*
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* Set interrupt mask register
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*/
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writel(0x00000000, &fec->eth->imask);
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/*
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* Clear FEC-Lite interrupt event register(IEVENT)
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*/
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writel(0xffffffff, &fec->eth->ievent);
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/*
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* Set FEC-Lite receive control register(R_CNTRL):
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*/
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/* Start with frame length = 1518, common for all modes. */
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rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
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if (fec->xcv_type != SEVENWIRE) /* xMII modes */
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rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
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if (fec->xcv_type == RGMII)
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rcntrl |= FEC_RCNTRL_RGMII;
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else if (fec->xcv_type == RMII)
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rcntrl |= FEC_RCNTRL_RMII;
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writel(rcntrl, &fec->eth->r_cntrl);
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}
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/**
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* Start the FEC engine
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* @param[in] dev Our device to handle
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*/
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static int fec_open(struct eth_device *edev)
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{
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struct fec_priv *fec = (struct fec_priv *)edev->priv;
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int speed;
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uint32_t addr, size;
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int i;
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debug("fec_open: fec_open(dev)\n");
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/* full-duplex, heartbeat disabled */
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writel(1 << 2, &fec->eth->x_cntrl);
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fec->rbd_index = 0;
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/* Invalidate all descriptors */
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for (i = 0; i < FEC_RBD_NUM - 1; i++)
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fec_rbd_clean(0, &fec->rbd_base[i]);
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fec_rbd_clean(1, &fec->rbd_base[i]);
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/* Flush the descriptors into RAM */
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size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
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ARCH_DMA_MINALIGN);
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addr = (uint32_t)fec->rbd_base;
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flush_dcache_range(addr, addr + size);
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#ifdef FEC_QUIRK_ENET_MAC
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/* Enable ENET HW endian SWAP */
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writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
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&fec->eth->ecntrl);
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/* Enable ENET store and forward mode */
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writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
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&fec->eth->x_wmrk);
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#endif
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/*
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* Enable FEC-Lite controller
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*/
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writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
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&fec->eth->ecntrl);
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#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
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udelay(100);
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/*
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* setup the MII gasket for RMII mode
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*/
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/* disable the gasket */
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writew(0, &fec->eth->miigsk_enr);
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/* wait for the gasket to be disabled */
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while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
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udelay(2);
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/* configure gasket for RMII, 50 MHz, no loopback, and no echo */
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writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
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/* re-enable the gasket */
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writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
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/* wait until MII gasket is ready */
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int max_loops = 10;
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while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
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if (--max_loops <= 0) {
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printf("WAIT for MII Gasket ready timed out\n");
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break;
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}
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}
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#endif
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#ifdef CONFIG_PHYLIB
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{
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/* Start up the PHY */
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int ret = phy_startup(fec->phydev);
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if (ret) {
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printf("Could not initialize PHY %s\n",
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fec->phydev->dev->name);
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return ret;
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}
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speed = fec->phydev->speed;
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}
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#else
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miiphy_wait_aneg(edev);
|
|
speed = miiphy_speed(edev->name, fec->phy_id);
|
|
miiphy_duplex(edev->name, fec->phy_id);
|
|
#endif
|
|
|
|
#ifdef FEC_QUIRK_ENET_MAC
|
|
{
|
|
u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
|
|
u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
|
|
if (speed == _1000BASET)
|
|
ecr |= FEC_ECNTRL_SPEED;
|
|
else if (speed != _100BASET)
|
|
rcr |= FEC_RCNTRL_RMII_10T;
|
|
writel(ecr, &fec->eth->ecntrl);
|
|
writel(rcr, &fec->eth->r_cntrl);
|
|
}
|
|
#endif
|
|
debug("%s:Speed=%i\n", __func__, speed);
|
|
|
|
/*
|
|
* Enable SmartDMA receive task
|
|
*/
|
|
fec_rx_task_enable(fec);
|
|
|
|
udelay(100000);
|
|
return 0;
|
|
}
|
|
|
|
static int fec_init(struct eth_device *dev, bd_t* bd)
|
|
{
|
|
struct fec_priv *fec = (struct fec_priv *)dev->priv;
|
|
uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
|
|
int i;
|
|
|
|
/* Initialize MAC address */
|
|
fec_set_hwaddr(dev);
|
|
|
|
/*
|
|
* Setup transmit descriptors, there are two in total.
|
|
*/
|
|
fec_tbd_init(fec);
|
|
|
|
/* Setup receive descriptors. */
|
|
fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
|
|
|
|
fec_reg_setup(fec);
|
|
|
|
if (fec->xcv_type != SEVENWIRE)
|
|
fec_mii_setspeed(fec->bus->priv);
|
|
|
|
/*
|
|
* Set Opcode/Pause Duration Register
|
|
*/
|
|
writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
|
|
writel(0x2, &fec->eth->x_wmrk);
|
|
/*
|
|
* Set multicast address filter
|
|
*/
|
|
writel(0x00000000, &fec->eth->gaddr1);
|
|
writel(0x00000000, &fec->eth->gaddr2);
|
|
|
|
|
|
/* clear MIB RAM */
|
|
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
|
|
writel(0, i);
|
|
|
|
/* FIFO receive start register */
|
|
writel(0x520, &fec->eth->r_fstart);
|
|
|
|
/* size and address of each buffer */
|
|
writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
|
|
writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
|
|
writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
|
|
|
|
#ifndef CONFIG_PHYLIB
|
|
if (fec->xcv_type != SEVENWIRE)
|
|
miiphy_restart_aneg(dev);
|
|
#endif
|
|
fec_open(dev);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Halt the FEC engine
|
|
* @param[in] dev Our device to handle
|
|
*/
|
|
static void fec_halt(struct eth_device *dev)
|
|
{
|
|
struct fec_priv *fec = (struct fec_priv *)dev->priv;
|
|
int counter = 0xffff;
|
|
|
|
/*
|
|
* issue graceful stop command to the FEC transmitter if necessary
|
|
*/
|
|
writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
|
|
&fec->eth->x_cntrl);
|
|
|
|
debug("eth_halt: wait for stop regs\n");
|
|
/*
|
|
* wait for graceful stop to register
|
|
*/
|
|
while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
|
|
udelay(1);
|
|
|
|
/*
|
|
* Disable SmartDMA tasks
|
|
*/
|
|
fec_tx_task_disable(fec);
|
|
fec_rx_task_disable(fec);
|
|
|
|
/*
|
|
* Disable the Ethernet Controller
|
|
* Note: this will also reset the BD index counter!
|
|
*/
|
|
writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
|
|
&fec->eth->ecntrl);
|
|
fec->rbd_index = 0;
|
|
fec->tbd_index = 0;
|
|
debug("eth_halt: done\n");
|
|
}
|
|
|
|
/**
|
|
* Transmit one frame
|
|
* @param[in] dev Our ethernet device to handle
|
|
* @param[in] packet Pointer to the data to be transmitted
|
|
* @param[in] length Data count in bytes
|
|
* @return 0 on success
|
|
*/
|
|
static int fec_send(struct eth_device *dev, void *packet, int length)
|
|
{
|
|
unsigned int status;
|
|
uint32_t size, end;
|
|
uint32_t addr;
|
|
int timeout = FEC_XFER_TIMEOUT;
|
|
int ret = 0;
|
|
|
|
/*
|
|
* This routine transmits one frame. This routine only accepts
|
|
* 6-byte Ethernet addresses.
|
|
*/
|
|
struct fec_priv *fec = (struct fec_priv *)dev->priv;
|
|
|
|
/*
|
|
* Check for valid length of data.
|
|
*/
|
|
if ((length > 1500) || (length <= 0)) {
|
|
printf("Payload (%d) too large\n", length);
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* Setup the transmit buffer. We are always using the first buffer for
|
|
* transmission, the second will be empty and only used to stop the DMA
|
|
* engine. We also flush the packet to RAM here to avoid cache trouble.
|
|
*/
|
|
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
|
|
swap_packet((uint32_t *)packet, length);
|
|
#endif
|
|
|
|
addr = (uint32_t)packet;
|
|
end = roundup(addr + length, ARCH_DMA_MINALIGN);
|
|
addr &= ~(ARCH_DMA_MINALIGN - 1);
|
|
flush_dcache_range(addr, end);
|
|
|
|
writew(length, &fec->tbd_base[fec->tbd_index].data_length);
|
|
writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
|
|
|
|
/*
|
|
* update BD's status now
|
|
* This block:
|
|
* - is always the last in a chain (means no chain)
|
|
* - should transmitt the CRC
|
|
* - might be the last BD in the list, so the address counter should
|
|
* wrap (-> keep the WRAP flag)
|
|
*/
|
|
status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
|
|
status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
|
|
writew(status, &fec->tbd_base[fec->tbd_index].status);
|
|
|
|
/*
|
|
* Flush data cache. This code flushes both TX descriptors to RAM.
|
|
* After this code, the descriptors will be safely in RAM and we
|
|
* can start DMA.
|
|
*/
|
|
size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
|
|
addr = (uint32_t)fec->tbd_base;
|
|
flush_dcache_range(addr, addr + size);
|
|
|
|
/*
|
|
* Below we read the DMA descriptor's last four bytes back from the
|
|
* DRAM. This is important in order to make sure that all WRITE
|
|
* operations on the bus that were triggered by previous cache FLUSH
|
|
* have completed.
|
|
*
|
|
* Otherwise, on MX28, it is possible to observe a corruption of the
|
|
* DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
|
|
* for the bus structure of MX28. The scenario is as follows:
|
|
*
|
|
* 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
|
|
* to DRAM due to flush_dcache_range()
|
|
* 2) ARM core writes the FEC registers via AHB_ARB2
|
|
* 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
|
|
*
|
|
* Note that 2) does sometimes finish before 1) due to reordering of
|
|
* WRITE accesses on the AHB bus, therefore triggering 3) before the
|
|
* DMA descriptor is fully written into DRAM. This results in occasional
|
|
* corruption of the DMA descriptor.
|
|
*/
|
|
readl(addr + size - 4);
|
|
|
|
/*
|
|
* Enable SmartDMA transmit task
|
|
*/
|
|
fec_tx_task_enable(fec);
|
|
|
|
/*
|
|
* Wait until frame is sent. On each turn of the wait cycle, we must
|
|
* invalidate data cache to see what's really in RAM. Also, we need
|
|
* barrier here.
|
|
*/
|
|
while (--timeout) {
|
|
if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
|
|
break;
|
|
}
|
|
|
|
if (!timeout)
|
|
ret = -EINVAL;
|
|
|
|
invalidate_dcache_range(addr, addr + size);
|
|
if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
|
|
ret = -EINVAL;
|
|
|
|
debug("fec_send: status 0x%x index %d ret %i\n",
|
|
readw(&fec->tbd_base[fec->tbd_index].status),
|
|
fec->tbd_index, ret);
|
|
/* for next transmission use the other buffer */
|
|
if (fec->tbd_index)
|
|
fec->tbd_index = 0;
|
|
else
|
|
fec->tbd_index = 1;
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* Pull one frame from the card
|
|
* @param[in] dev Our ethernet device to handle
|
|
* @return Length of packet read
|
|
*/
|
|
static int fec_recv(struct eth_device *dev)
|
|
{
|
|
struct fec_priv *fec = (struct fec_priv *)dev->priv;
|
|
struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
|
|
unsigned long ievent;
|
|
int frame_length, len = 0;
|
|
struct nbuf *frame;
|
|
uint16_t bd_status;
|
|
uint32_t addr, size, end;
|
|
int i;
|
|
ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
|
|
|
|
/*
|
|
* Check if any critical events have happened
|
|
*/
|
|
ievent = readl(&fec->eth->ievent);
|
|
writel(ievent, &fec->eth->ievent);
|
|
debug("fec_recv: ievent 0x%lx\n", ievent);
|
|
if (ievent & FEC_IEVENT_BABR) {
|
|
fec_halt(dev);
|
|
fec_init(dev, fec->bd);
|
|
printf("some error: 0x%08lx\n", ievent);
|
|
return 0;
|
|
}
|
|
if (ievent & FEC_IEVENT_HBERR) {
|
|
/* Heartbeat error */
|
|
writel(0x00000001 | readl(&fec->eth->x_cntrl),
|
|
&fec->eth->x_cntrl);
|
|
}
|
|
if (ievent & FEC_IEVENT_GRA) {
|
|
/* Graceful stop complete */
|
|
if (readl(&fec->eth->x_cntrl) & 0x00000001) {
|
|
fec_halt(dev);
|
|
writel(~0x00000001 & readl(&fec->eth->x_cntrl),
|
|
&fec->eth->x_cntrl);
|
|
fec_init(dev, fec->bd);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Read the buffer status. Before the status can be read, the data cache
|
|
* must be invalidated, because the data in RAM might have been changed
|
|
* by DMA. The descriptors are properly aligned to cachelines so there's
|
|
* no need to worry they'd overlap.
|
|
*
|
|
* WARNING: By invalidating the descriptor here, we also invalidate
|
|
* the descriptors surrounding this one. Therefore we can NOT change the
|
|
* contents of this descriptor nor the surrounding ones. The problem is
|
|
* that in order to mark the descriptor as processed, we need to change
|
|
* the descriptor. The solution is to mark the whole cache line when all
|
|
* descriptors in the cache line are processed.
|
|
*/
|
|
addr = (uint32_t)rbd;
|
|
addr &= ~(ARCH_DMA_MINALIGN - 1);
|
|
size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
|
|
invalidate_dcache_range(addr, addr + size);
|
|
|
|
bd_status = readw(&rbd->status);
|
|
debug("fec_recv: status 0x%x\n", bd_status);
|
|
|
|
if (!(bd_status & FEC_RBD_EMPTY)) {
|
|
if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
|
|
((readw(&rbd->data_length) - 4) > 14)) {
|
|
/*
|
|
* Get buffer address and size
|
|
*/
|
|
frame = (struct nbuf *)readl(&rbd->data_pointer);
|
|
frame_length = readw(&rbd->data_length) - 4;
|
|
/*
|
|
* Invalidate data cache over the buffer
|
|
*/
|
|
addr = (uint32_t)frame;
|
|
end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
|
|
addr &= ~(ARCH_DMA_MINALIGN - 1);
|
|
invalidate_dcache_range(addr, end);
|
|
|
|
/*
|
|
* Fill the buffer and pass it to upper layers
|
|
*/
|
|
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
|
|
swap_packet((uint32_t *)frame->data, frame_length);
|
|
#endif
|
|
memcpy(buff, frame->data, frame_length);
|
|
NetReceive(buff, frame_length);
|
|
len = frame_length;
|
|
} else {
|
|
if (bd_status & FEC_RBD_ERR)
|
|
printf("error frame: 0x%08lx 0x%08x\n",
|
|
(ulong)rbd->data_pointer,
|
|
bd_status);
|
|
}
|
|
|
|
/*
|
|
* Free the current buffer, restart the engine and move forward
|
|
* to the next buffer. Here we check if the whole cacheline of
|
|
* descriptors was already processed and if so, we mark it free
|
|
* as whole.
|
|
*/
|
|
size = RXDESC_PER_CACHELINE - 1;
|
|
if ((fec->rbd_index & size) == size) {
|
|
i = fec->rbd_index - size;
|
|
addr = (uint32_t)&fec->rbd_base[i];
|
|
for (; i <= fec->rbd_index ; i++) {
|
|
fec_rbd_clean(i == (FEC_RBD_NUM - 1),
|
|
&fec->rbd_base[i]);
|
|
}
|
|
flush_dcache_range(addr,
|
|
addr + ARCH_DMA_MINALIGN);
|
|
}
|
|
|
|
fec_rx_task_enable(fec);
|
|
fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
|
|
}
|
|
debug("fec_recv: stop\n");
|
|
|
|
return len;
|
|
}
|
|
|
|
static void fec_set_dev_name(char *dest, int dev_id)
|
|
{
|
|
sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
|
|
}
|
|
|
|
static int fec_alloc_descs(struct fec_priv *fec)
|
|
{
|
|
unsigned int size;
|
|
int i;
|
|
uint8_t *data;
|
|
|
|
/* Allocate TX descriptors. */
|
|
size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
|
|
fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
|
|
if (!fec->tbd_base)
|
|
goto err_tx;
|
|
|
|
/* Allocate RX descriptors. */
|
|
size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
|
|
fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
|
|
if (!fec->rbd_base)
|
|
goto err_rx;
|
|
|
|
memset(fec->rbd_base, 0, size);
|
|
|
|
/* Allocate RX buffers. */
|
|
|
|
/* Maximum RX buffer size. */
|
|
size = roundup(FEC_MAX_PKT_SIZE, ARCH_DMA_MINALIGN);
|
|
for (i = 0; i < FEC_RBD_NUM; i++) {
|
|
data = memalign(ARCH_DMA_MINALIGN, size);
|
|
if (!data) {
|
|
printf("%s: error allocating rxbuf %d\n", __func__, i);
|
|
goto err_ring;
|
|
}
|
|
|
|
memset(data, 0, size);
|
|
|
|
fec->rbd_base[i].data_pointer = (uint32_t)data;
|
|
fec->rbd_base[i].status = FEC_RBD_EMPTY;
|
|
fec->rbd_base[i].data_length = 0;
|
|
/* Flush the buffer to memory. */
|
|
flush_dcache_range((uint32_t)data, (uint32_t)data + size);
|
|
}
|
|
|
|
/* Mark the last RBD to close the ring. */
|
|
fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
|
|
|
|
fec->rbd_index = 0;
|
|
fec->tbd_index = 0;
|
|
|
|
return 0;
|
|
|
|
err_ring:
|
|
for (; i >= 0; i--)
|
|
free((void *)fec->rbd_base[i].data_pointer);
|
|
free(fec->rbd_base);
|
|
err_rx:
|
|
free(fec->tbd_base);
|
|
err_tx:
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static void fec_free_descs(struct fec_priv *fec)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < FEC_RBD_NUM; i++)
|
|
free((void *)fec->rbd_base[i].data_pointer);
|
|
free(fec->rbd_base);
|
|
free(fec->tbd_base);
|
|
}
|
|
|
|
#ifdef CONFIG_PHYLIB
|
|
int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
|
|
struct mii_dev *bus, struct phy_device *phydev)
|
|
#else
|
|
static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
|
|
struct mii_dev *bus, int phy_id)
|
|
#endif
|
|
{
|
|
struct eth_device *edev;
|
|
struct fec_priv *fec;
|
|
unsigned char ethaddr[6];
|
|
uint32_t start;
|
|
int ret = 0;
|
|
|
|
/* create and fill edev struct */
|
|
edev = (struct eth_device *)malloc(sizeof(struct eth_device));
|
|
if (!edev) {
|
|
puts("fec_mxc: not enough malloc memory for eth_device\n");
|
|
ret = -ENOMEM;
|
|
goto err1;
|
|
}
|
|
|
|
fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
|
|
if (!fec) {
|
|
puts("fec_mxc: not enough malloc memory for fec_priv\n");
|
|
ret = -ENOMEM;
|
|
goto err2;
|
|
}
|
|
|
|
memset(edev, 0, sizeof(*edev));
|
|
memset(fec, 0, sizeof(*fec));
|
|
|
|
ret = fec_alloc_descs(fec);
|
|
if (ret)
|
|
goto err3;
|
|
|
|
edev->priv = fec;
|
|
edev->init = fec_init;
|
|
edev->send = fec_send;
|
|
edev->recv = fec_recv;
|
|
edev->halt = fec_halt;
|
|
edev->write_hwaddr = fec_set_hwaddr;
|
|
|
|
fec->eth = (struct ethernet_regs *)base_addr;
|
|
fec->bd = bd;
|
|
|
|
fec->xcv_type = CONFIG_FEC_XCV_TYPE;
|
|
|
|
/* Reset chip. */
|
|
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
|
|
start = get_timer(0);
|
|
while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
|
|
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
|
|
printf("FEC MXC: Timeout reseting chip\n");
|
|
goto err4;
|
|
}
|
|
udelay(10);
|
|
}
|
|
|
|
fec_reg_setup(fec);
|
|
fec_set_dev_name(edev->name, dev_id);
|
|
fec->dev_id = (dev_id == -1) ? 0 : dev_id;
|
|
fec->bus = bus;
|
|
fec_mii_setspeed(bus->priv);
|
|
#ifdef CONFIG_PHYLIB
|
|
fec->phydev = phydev;
|
|
phy_connect_dev(phydev, edev);
|
|
/* Configure phy */
|
|
phy_config(phydev);
|
|
#else
|
|
fec->phy_id = phy_id;
|
|
#endif
|
|
eth_register(edev);
|
|
|
|
if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
|
|
debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
|
|
memcpy(edev->enetaddr, ethaddr, 6);
|
|
if (!getenv("ethaddr"))
|
|
eth_setenv_enetaddr("ethaddr", ethaddr);
|
|
}
|
|
return ret;
|
|
err4:
|
|
fec_free_descs(fec);
|
|
err3:
|
|
free(fec);
|
|
err2:
|
|
free(edev);
|
|
err1:
|
|
return ret;
|
|
}
|
|
|
|
struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
|
|
{
|
|
struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
|
|
struct mii_dev *bus;
|
|
int ret;
|
|
|
|
bus = mdio_alloc();
|
|
if (!bus) {
|
|
printf("mdio_alloc failed\n");
|
|
return NULL;
|
|
}
|
|
bus->read = fec_phy_read;
|
|
bus->write = fec_phy_write;
|
|
bus->priv = eth;
|
|
fec_set_dev_name(bus->name, dev_id);
|
|
|
|
ret = mdio_register(bus);
|
|
if (ret) {
|
|
printf("mdio_register failed\n");
|
|
free(bus);
|
|
return NULL;
|
|
}
|
|
fec_mii_setspeed(eth);
|
|
return bus;
|
|
}
|
|
|
|
int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
|
|
{
|
|
uint32_t base_mii;
|
|
struct mii_dev *bus = NULL;
|
|
#ifdef CONFIG_PHYLIB
|
|
struct phy_device *phydev = NULL;
|
|
#endif
|
|
int ret;
|
|
|
|
#ifdef CONFIG_MX28
|
|
/*
|
|
* The i.MX28 has two ethernet interfaces, but they are not equal.
|
|
* Only the first one can access the MDIO bus.
|
|
*/
|
|
base_mii = MXS_ENET0_BASE;
|
|
#else
|
|
base_mii = addr;
|
|
#endif
|
|
debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
|
|
bus = fec_get_miibus(base_mii, dev_id);
|
|
if (!bus)
|
|
return -ENOMEM;
|
|
#ifdef CONFIG_PHYLIB
|
|
phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
|
|
if (!phydev) {
|
|
free(bus);
|
|
return -ENOMEM;
|
|
}
|
|
ret = fec_probe(bd, dev_id, addr, bus, phydev);
|
|
#else
|
|
ret = fec_probe(bd, dev_id, addr, bus, phy_id);
|
|
#endif
|
|
if (ret) {
|
|
#ifdef CONFIG_PHYLIB
|
|
free(phydev);
|
|
#endif
|
|
free(bus);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_FEC_MXC_PHYADDR
|
|
int fecmxc_initialize(bd_t *bd)
|
|
{
|
|
return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
|
|
IMX_FEC_BASE);
|
|
}
|
|
#endif
|
|
|
|
#ifndef CONFIG_PHYLIB
|
|
int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
|
|
{
|
|
struct fec_priv *fec = (struct fec_priv *)dev->priv;
|
|
fec->mii_postcall = cb;
|
|
return 0;
|
|
}
|
|
#endif
|