u-boot/arch/arm/dts/rz-g2-beacon-u-boot.dtsi
Adam Ford edd9c891d2 arm: dts: rz-g2-beacon-u-boot: Fix QSPI Regression
The QSPI is accessed via the RPC-IF, but the compatible flags
previously used a different name.  This compatibel name was changed
which broke the ability to access the QSPI.  Fix this by removing
the custom naming reference.

Fixes: 68083b897b ("renesas: Fix RPC-IF compatible values")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
2023-01-06 08:14:19 -05:00

83 lines
1.1 KiB
Text

// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2021 LogicPD dba Beacon EmbeddedWorks
*/
/ {
aliases {
spi0 = &rpc;
};
soc {
u-boot,dm-pre-reloc;
};
};
&cpg {
u-boot,dm-pre-reloc;
};
&ehci0 {
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
};
&ehci1 {
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
};
&extal_clk {
u-boot,dm-pre-reloc;
};
&extalr_clk {
u-boot,dm-pre-reloc;
};
&pfc {
qspi_pins: qspi {
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
};
&prr {
u-boot,dm-pre-reloc;
};
&rpc {
pinctrl-0 = <&qspi_pins>;
pinctrl-names = "default";
num-cs = <1>;
spi-max-frequency = <40000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
compatible = "spi-flash", "jedec,spi-nor";
spi-max-frequency = <40000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
&sdhi0 {
/delete-property/ cd-gpios;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr104;
max-frequency = <208000000>;
};
&sdhi2 {
status = "disabled";
};
&sdhi3 {
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
};