mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-15 07:43:07 +00:00
1332a781e1
Xilinx is using standard mtd partition layout for quite a long time. It is used for testing purpose on evaluation boards. Also #address/size-cells shouldn't be present without nodes which should use them that's why move them from zynq-7000.dtsi to nand/nor nodes directly. The patch was tested on zc706 and zedboard(with also increasing max frequency and rx bus width). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/4c3348981bba32d3892194420d78fe8621c47534.1698837725.git.michal.simek@amd.com
104 lines
1.7 KiB
Text
104 lines
1.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011 - 2015 Xilinx
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* Copyright (C) 2012 National Instruments Corp.
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*/
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/dts-v1/;
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#include "zynq-7000.dtsi"
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/ {
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model = "Avnet ZedBoard board";
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compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000";
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aliases {
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ethernet0 = &gem0;
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serial0 = &uart1;
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spi0 = &qspi;
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mmc0 = &sdhci0;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x20000000>;
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};
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chosen {
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bootargs = "";
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stdout-path = "serial0:115200n8";
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};
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usb_phy0: phy0 {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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};
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};
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&clkc {
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ps-clk-frequency = <33333333>;
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};
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&gem0 {
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status = "okay";
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phy-mode = "rgmii-id";
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phy-handle = <ðernet_phy>;
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ethernet_phy: ethernet-phy@0 {
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reg = <0>;
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device_type = "ethernet-phy";
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};
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};
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&qspi {
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bootph-all;
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status = "okay";
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num-cs = <1>;
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flash@0 {
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compatible = "spansion,s25fl256s1", "jedec,spi-nor";
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reg = <0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "qspi-fsbl-uboot";
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reg = <0x0 0x100000>;
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};
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partition@100000 {
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label = "qspi-linux";
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reg = <0x100000 0x500000>;
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};
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partition@600000 {
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label = "qspi-device-tree";
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reg = <0x600000 0x20000>;
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};
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partition@620000 {
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label = "qspi-rootfs";
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reg = <0x620000 0x5e0000>;
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};
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partition@c00000 {
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label = "qspi-bitstream";
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reg = <0xc00000 0x400000>;
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};
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};
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};
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};
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&sdhci0 {
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bootph-all;
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status = "okay";
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};
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&uart1 {
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bootph-all;
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status = "okay";
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};
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&usb0 {
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status = "okay";
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dr_mode = "host";
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usb-phy = <&usb_phy0>;
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};
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