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https://github.com/AsahiLinux/u-boot
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497db3ad89
The uart1 node was missing the 'clock-frequency' property. This meant the driver for this device would fail at probe. The clock for uart1 is fed from the same source as uart0 and is a fixed 200MHz clock. This is confirmed via documentation for the CN9130 SoC and from the equivalent code in Linux at: <linux>/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi where uart0 and uart1 share a common 'clocks' definition. Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Reviewed-by: Stefan Roese <sr@denx.de>
211 lines
4.8 KiB
Text
211 lines
4.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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*/
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/*
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* Device Tree file for Marvell Armada AP806/AP807.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/dts-v1/;
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/ {
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compatible = "marvell,armada-ap806";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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psci-area@4000000 {
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reg = <0x0 0x4000000 0x0 0x200000>;
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no-map;
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};
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};
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AP_NAME {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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config-space {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x0 0x0 0xf0000000 0x1000000>;
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gic: interrupt-controller@210000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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reg = <0x210000 0x10000>,
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<0x220000 0x20000>,
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<0x240000 0x20000>,
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<0x260000 0x20000>;
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gic_v2m0: v2m@280000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x280000 0x1000>;
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arm,msi-base-spi = <160>;
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arm,msi-num-spis = <32>;
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};
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gic_v2m1: v2m@290000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x290000 0x1000>;
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arm,msi-base-spi = <192>;
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arm,msi-num-spis = <32>;
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};
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gic_v2m2: v2m@2a0000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x2a0000 0x1000>;
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arm,msi-base-spi = <224>;
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arm,msi-num-spis = <32>;
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};
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gic_v2m3: v2m@2b0000 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x2b0000 0x1000>;
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arm,msi-base-spi = <256>;
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arm,msi-num-spis = <32>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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};
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odmi: odmi@300000 {
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compatible = "marvell,odmi-controller";
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interrupt-controller;
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msi-controller;
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marvell,odmi-frames = <4>;
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reg = <0x300000 0x4000>,
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<0x304000 0x4000>,
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<0x308000 0x4000>,
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<0x30C000 0x4000>;
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marvell,spi-base = <128>, <136>, <144>, <152>;
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};
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ap_pinctl: ap-pinctl@6F4000 {
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compatible = "marvell,ap806-pinctrl";
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bank-name ="apn-806";
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reg = <0x6F4000 0x10>;
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pin-count = <20>;
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max-func = <3>;
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ap_i2c0_pins: i2c-pins-0 {
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marvell,pins = < 4 5 >;
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marvell,function = <3>;
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};
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ap_emmc_pins: emmc-pins-0 {
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marvell,pins = < 0 1 2 3 4 5 6 7
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8 9 10 12 >;
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marvell,function = <1>;
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};
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};
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ap_gpio0: gpio@6F5040 {
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compatible = "marvell,orion-gpio";
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reg = <0x6F5040 0x40>;
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ngpios = <20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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ap_spi0: spi@510600 {
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compatible = "marvell,armada-380-spi";
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reg = <0x510600 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ap_syscon 3>;
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status = "disabled";
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};
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ap_i2c0: i2c@511000 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x511000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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timeout-ms = <1000>;
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clocks = <&ap_syscon 3>;
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status = "disabled";
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};
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uart0: serial@512000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x512000 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&ap_syscon 3>;
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status = "disabled";
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clock-frequency = <200000000>;
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};
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uart1: serial@512100 {
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compatible = "snps,dw-apb-uart";
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reg = <0x512100 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&ap_syscon 3>;
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status = "disabled";
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clock-frequency = <200000000>;
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};
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watchdog: watchdog@610000 {
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compatible = "arm,sbsa-gwdt";
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reg = <0x610000 0x1000>, <0x600000 0x1000>;
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};
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ap_sdhci0: sdhci@6e0000 {
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compatible = "marvell,armada-8k-sdhci";
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reg = <0x6e0000 0x300>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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dma-coherent;
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status = "disabled";
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};
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ap_syscon: system-controller@6f4000 {
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compatible = "marvell,ap806-system-controller",
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"syscon";
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#clock-cells = <1>;
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clock-output-names = "ap-cpu-cluster-0",
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"ap-cpu-cluster-1",
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"ap-fixed", "ap-mss";
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reg = <0x6f4000 0x1000>;
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};
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};
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};
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};
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