mirror of
https://github.com/AsahiLinux/u-boot
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218539e2e7
If the fifo-size DT parameter is not provided then probe the controller's fifo depth at runtime. This is ported from a patch in the Linux Xilinx SPI driver. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/1422029330-10971-5-git-send-email-ricardo.ribalda@gmail.com Tested-by: Love Kumar <love.kumar@amd.com> Link: https://lore.kernel.org/r/20231116164336.140171-4-mchitale@ventanamicro.com Signed-off-by: Michal Simek <michal.simek@amd.com>
484 lines
12 KiB
C
484 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Xilinx SPI driver
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*
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* Supports 8 bit SPI transfers only, with or w/o FIFO
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*
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* Based on bfin_spi.c, by way of altera_spi.c
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* Copyright (c) 2015 Jagan Teki <jteki@openedev.com>
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* Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
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* Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
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* Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*/
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#include <config.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <malloc.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <asm/io.h>
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#include <wait_bit.h>
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#include <linux/bitops.h>
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/*
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* [0]: http://www.xilinx.com/support/documentation
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*
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* Xilinx SPI Register Definitions
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* [1]: [0]/ip_documentation/xps_spi.pdf
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* page 8, Register Descriptions
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* [2]: [0]/ip_documentation/axi_spi_ds742.pdf
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* page 7, Register Overview Table
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*/
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/* SPI Control Register (spicr), [1] p9, [2] p8 */
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#define SPICR_LSB_FIRST BIT(9)
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#define SPICR_MASTER_INHIBIT BIT(8)
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#define SPICR_MANUAL_SS BIT(7)
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#define SPICR_RXFIFO_RESEST BIT(6)
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#define SPICR_TXFIFO_RESEST BIT(5)
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#define SPICR_CPHA BIT(4)
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#define SPICR_CPOL BIT(3)
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#define SPICR_MASTER_MODE BIT(2)
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#define SPICR_SPE BIT(1)
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#define SPICR_LOOP BIT(0)
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/* SPI Status Register (spisr), [1] p11, [2] p10 */
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#define SPISR_SLAVE_MODE_SELECT BIT(5)
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#define SPISR_MODF BIT(4)
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#define SPISR_TX_FULL BIT(3)
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#define SPISR_TX_EMPTY BIT(2)
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#define SPISR_RX_FULL BIT(1)
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#define SPISR_RX_EMPTY BIT(0)
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/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
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#define SPIDTR_8BIT_MASK GENMASK(7, 0)
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#define SPIDTR_16BIT_MASK GENMASK(15, 0)
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#define SPIDTR_32BIT_MASK GENMASK(31, 0)
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/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
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#define SPIDRR_8BIT_MASK GENMASK(7, 0)
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#define SPIDRR_16BIT_MASK GENMASK(15, 0)
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#define SPIDRR_32BIT_MASK GENMASK(31, 0)
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/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
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#define SPISSR_MASK(cs) (1 << (cs))
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#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
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#define SPISSR_OFF (~0U)
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/* SPI Software Reset Register (ssr) */
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#define SPISSR_RESET_VALUE 0x0a
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#define XILSPI_MAX_XFER_BITS 8
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#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
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SPICR_SPE | SPICR_MASTER_INHIBIT)
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#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
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#define XILINX_SPI_IDLE_VAL GENMASK(7, 0)
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#define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */
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/* xilinx spi register set */
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struct xilinx_spi_regs {
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u32 __space0__[7];
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u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
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u32 ipisr; /* IP Interrupt Status Register (IPISR) */
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u32 __space1__;
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u32 ipier; /* IP Interrupt Enable Register (IPIER) */
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u32 __space2__[5];
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u32 srr; /* Softare Reset Register (SRR) */
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u32 __space3__[7];
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u32 spicr; /* SPI Control Register (SPICR) */
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u32 spisr; /* SPI Status Register (SPISR) */
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u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
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u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
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u32 spissr; /* SPI Slave Select Register (SPISSR) */
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u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
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u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
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};
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/* xilinx spi priv */
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struct xilinx_spi_priv {
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struct xilinx_spi_regs *regs;
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unsigned int freq;
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unsigned int mode;
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unsigned int fifo_depth;
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u8 startup;
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};
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static int xilinx_spi_find_buffer_size(struct xilinx_spi_regs *regs)
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{
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u8 sr;
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int n_words = 0;
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/*
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* Before the buffer_size detection reset the core
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* to make sure to start with a clean state.
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*/
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writel(SPISSR_RESET_VALUE, ®s->srr);
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/* Fill the Tx FIFO with as many words as possible */
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do {
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writel(0, ®s->spidtr);
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sr = readl(®s->spisr);
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n_words++;
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} while (!(sr & SPISR_TX_FULL));
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return n_words;
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}
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static int xilinx_spi_probe(struct udevice *bus)
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{
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs;
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regs = priv->regs = dev_read_addr_ptr(bus);
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priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
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if (!priv->fifo_depth)
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priv->fifo_depth = xilinx_spi_find_buffer_size(regs);
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writel(SPISSR_RESET_VALUE, ®s->srr);
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/*
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* Reset RX & TX FIFO
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* Enable Manual Slave Select Assertion,
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* Set SPI controller into master mode, and enable it
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*/
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writel(SPICR_RXFIFO_RESEST | SPICR_TXFIFO_RESEST |
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SPICR_MANUAL_SS | SPICR_MASTER_MODE | SPICR_SPE,
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®s->spicr);
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return 0;
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}
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static void spi_cs_activate(struct udevice *dev, uint cs)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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writel(SPISSR_ACT(cs), ®s->spissr);
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}
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static void spi_cs_deactivate(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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u32 reg;
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reg = readl(®s->spicr) | SPICR_RXFIFO_RESEST | SPICR_TXFIFO_RESEST;
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writel(reg, ®s->spicr);
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writel(SPISSR_OFF, ®s->spissr);
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}
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static int xilinx_spi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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writel(SPISSR_OFF, ®s->spissr);
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writel(XILSPI_SPICR_DFLT_ON, ®s->spicr);
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return 0;
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}
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static int xilinx_spi_release_bus(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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writel(SPISSR_OFF, ®s->spissr);
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writel(XILSPI_SPICR_DFLT_OFF, ®s->spicr);
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return 0;
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}
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static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
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u32 txbytes)
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{
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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unsigned char d;
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u32 i = 0;
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while (txbytes && !(readl(®s->spisr) & SPISR_TX_FULL) &&
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i < priv->fifo_depth) {
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d = txp ? *txp++ : XILINX_SPI_IDLE_VAL;
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debug("spi_xfer: tx:%x ", d);
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/* write out and wait for processing (receive data) */
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writel(d & SPIDTR_8BIT_MASK, ®s->spidtr);
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txbytes--;
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i++;
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}
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return i;
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}
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static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
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{
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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unsigned char d;
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unsigned int i = 0;
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while (rxbytes && !(readl(®s->spisr) & SPISR_RX_EMPTY)) {
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d = readl(®s->spidrr) & SPIDRR_8BIT_MASK;
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if (rxp)
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*rxp++ = d;
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debug("spi_xfer: rx:%x\n", d);
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rxbytes--;
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i++;
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}
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debug("Rx_done\n");
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return i;
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}
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static int start_transfer(struct udevice *dev, const void *dout, void *din, u32 len)
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{
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struct udevice *bus = dev->parent;
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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u32 count, txbytes, rxbytes;
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int reg, ret;
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const unsigned char *txp = (const unsigned char *)dout;
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unsigned char *rxp = (unsigned char *)din;
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txbytes = len;
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rxbytes = len;
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while (txbytes || rxbytes) {
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/* Disable master transaction */
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reg = readl(®s->spicr) | SPICR_MASTER_INHIBIT;
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writel(reg, ®s->spicr);
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count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
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/* Enable master transaction */
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reg = readl(®s->spicr) & ~SPICR_MASTER_INHIBIT;
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writel(reg, ®s->spicr);
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txbytes -= count;
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if (txp)
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txp += count;
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ret = wait_for_bit_le32(®s->spisr, SPISR_TX_EMPTY, true,
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XILINX_SPISR_TIMEOUT, false);
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if (ret < 0) {
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printf("XILSPI error: Xfer timeout\n");
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return ret;
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}
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reg = readl(®s->spicr) | SPICR_MASTER_INHIBIT;
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writel(reg, ®s->spicr);
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count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
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rxbytes -= count;
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if (rxp)
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rxp += count;
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}
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return 0;
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}
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static void xilinx_spi_startup_block(struct udevice *dev)
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{
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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unsigned char txp;
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unsigned char rxp[8];
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/*
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* Perform a dummy read as a work around for
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* the startup block issue.
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*/
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spi_cs_activate(dev, slave_plat->cs);
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txp = 0x9f;
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start_transfer(dev, (void *)&txp, NULL, 1);
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start_transfer(dev, NULL, (void *)rxp, 6);
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spi_cs_deactivate(dev);
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}
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static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
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int ret;
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spi_cs_activate(dev, slave_plat->cs);
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ret = start_transfer(dev, dout, din, bitlen / 8);
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spi_cs_deactivate(dev);
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return ret;
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}
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static int xilinx_spi_mem_exec_op(struct spi_slave *spi,
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const struct spi_mem_op *op)
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{
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struct dm_spi_slave_plat *slave_plat =
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dev_get_parent_plat(spi->dev);
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static u32 startup;
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u32 dummy_len, ret;
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/*
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* This is the work around for the startup block issue in
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* the spi controller. SPI clock is passing through STARTUP
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* block to FLASH. STARTUP block don't provide clock as soon
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* as QSPI provides command. So first command fails.
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*/
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if (!startup) {
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xilinx_spi_startup_block(spi->dev);
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startup++;
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}
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spi_cs_activate(spi->dev, slave_plat->cs);
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if (op->cmd.opcode) {
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ret = start_transfer(spi->dev, (void *)&op->cmd.opcode,
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NULL, 1);
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if (ret)
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goto done;
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}
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if (op->addr.nbytes) {
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int i;
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u8 addr_buf[4];
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for (i = 0; i < op->addr.nbytes; i++)
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addr_buf[i] = op->addr.val >>
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(8 * (op->addr.nbytes - i - 1));
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ret = start_transfer(spi->dev, (void *)addr_buf, NULL,
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op->addr.nbytes);
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if (ret)
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goto done;
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}
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if (op->dummy.nbytes) {
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dummy_len = (op->dummy.nbytes * op->data.buswidth) /
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op->dummy.buswidth;
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ret = start_transfer(spi->dev, NULL, NULL, dummy_len);
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if (ret)
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goto done;
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}
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if (op->data.nbytes) {
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if (op->data.dir == SPI_MEM_DATA_IN) {
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ret = start_transfer(spi->dev, NULL,
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op->data.buf.in, op->data.nbytes);
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} else {
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ret = start_transfer(spi->dev, op->data.buf.out,
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NULL, op->data.nbytes);
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}
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if (ret)
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goto done;
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}
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done:
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spi_cs_deactivate(spi->dev);
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return ret;
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}
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static int xilinx_qspi_check_buswidth(struct spi_slave *slave, u8 width)
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{
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u32 mode = slave->mode;
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switch (width) {
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case 1:
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return 0;
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case 2:
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if (mode & SPI_RX_DUAL)
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return 0;
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break;
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case 4:
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if (mode & SPI_RX_QUAD)
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return 0;
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break;
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}
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return -EOPNOTSUPP;
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}
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static bool xilinx_qspi_mem_exec_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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if (xilinx_qspi_check_buswidth(slave, op->cmd.buswidth))
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return false;
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if (op->addr.nbytes &&
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xilinx_qspi_check_buswidth(slave, op->addr.buswidth))
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return false;
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if (op->dummy.nbytes &&
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xilinx_qspi_check_buswidth(slave, op->dummy.buswidth))
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return false;
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if (op->data.dir != SPI_MEM_NO_DATA &&
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xilinx_qspi_check_buswidth(slave, op->data.buswidth))
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return false;
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return true;
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}
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static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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priv->freq = speed;
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debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
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return 0;
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}
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static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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u32 spicr;
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spicr = readl(®s->spicr);
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if (mode & SPI_LSB_FIRST)
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spicr |= SPICR_LSB_FIRST;
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if (mode & SPI_CPHA)
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spicr |= SPICR_CPHA;
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if (mode & SPI_CPOL)
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spicr |= SPICR_CPOL;
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if (mode & SPI_LOOP)
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spicr |= SPICR_LOOP;
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writel(spicr, ®s->spicr);
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priv->mode = mode;
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debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
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return 0;
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}
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static const struct spi_controller_mem_ops xilinx_spi_mem_ops = {
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.exec_op = xilinx_spi_mem_exec_op,
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.supports_op = xilinx_qspi_mem_exec_op,
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};
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static const struct dm_spi_ops xilinx_spi_ops = {
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.claim_bus = xilinx_spi_claim_bus,
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.release_bus = xilinx_spi_release_bus,
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.xfer = xilinx_spi_xfer,
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.set_speed = xilinx_spi_set_speed,
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.set_mode = xilinx_spi_set_mode,
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.mem_ops = &xilinx_spi_mem_ops,
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};
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static const struct udevice_id xilinx_spi_ids[] = {
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{ .compatible = "xlnx,xps-spi-2.00.a" },
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{ .compatible = "xlnx,xps-spi-2.00.b" },
|
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{ }
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};
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|
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U_BOOT_DRIVER(xilinx_spi) = {
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.name = "xilinx_spi",
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.id = UCLASS_SPI,
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.of_match = xilinx_spi_ids,
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.ops = &xilinx_spi_ops,
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.priv_auto = sizeof(struct xilinx_spi_priv),
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.probe = xilinx_spi_probe,
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};
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