mirror of
https://github.com/AsahiLinux/u-boot
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6e7df1d151
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
235 lines
6.7 KiB
C
235 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010 - 2011
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/flow.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/apb_misc.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/warmboot.h>
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#include "warmboot_avp.h"
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#define DEBUG_RESET_CORESIGHT
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void wb_start(void)
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{
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struct apb_misc_pp_ctlr *apb_misc =
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(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
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struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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union osc_ctrl_reg osc_ctrl;
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union pllx_base_reg pllx_base;
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union pllx_misc_reg pllx_misc;
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union scratch3_reg scratch3;
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u32 reg;
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/* enable JTAG & TBE */
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writel(CFG_CTL_TBE | CFG_CTL_JTAG, &apb_misc->cfg_ctl);
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/* Are we running where we're supposed to be? */
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asm volatile (
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"adr %0, wb_start;" /* reg: wb_start address */
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: "=r"(reg) /* output */
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/* no input, no clobber list */
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);
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if (reg != NV_WB_RUN_ADDRESS)
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goto do_reset;
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/* Are we running with AVP? */
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if (readl(NV_PA_PG_UP_BASE + PG_UP_TAG_0) != PG_UP_TAG_AVP)
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goto do_reset;
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#ifdef DEBUG_RESET_CORESIGHT
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/* Assert CoreSight reset */
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reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);
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reg |= SWR_CSITE_RST;
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writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);
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#endif
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/* TODO: Set the drive strength - maybe make this a board parameter? */
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osc_ctrl.word = readl(&clkrst->crc_osc_ctrl);
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osc_ctrl.xofs = 4;
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osc_ctrl.xoe = 1;
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writel(osc_ctrl.word, &clkrst->crc_osc_ctrl);
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/* Power up the CPU complex if necessary */
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if (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) {
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reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START;
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writel(reg, &pmc->pmc_pwrgate_toggle);
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while (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU))
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;
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}
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/* Remove the I/O clamps from the CPU power partition. */
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reg = readl(&pmc->pmc_remove_clamping);
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reg |= CPU_CLMP;
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writel(reg, &pmc->pmc_remove_clamping);
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reg = EVENT_ZERO_VAL_20 | EVENT_MSEC | EVENT_MODE_STOP;
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writel(reg, &flow->halt_cop_events);
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/* Assert CPU complex reset */
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reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);
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reg |= CPU_RST;
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writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
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/* Hold both CPUs in reset */
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reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_CPURESET1 | CPU_CMPLX_DERESET0 |
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CPU_CMPLX_DERESET1 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DBGRESET1;
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writel(reg, &clkrst->crc_cpu_cmplx_set);
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/* Halt CPU1 at the flow controller for uni-processor configurations */
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writel(EVENT_MODE_STOP, &flow->halt_cpu1_events);
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/*
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* Set the CPU reset vector. SCRATCH41 contains the physical
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* address of the CPU-side restoration code.
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*/
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reg = readl(&pmc->pmc_scratch41);
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writel(reg, EXCEP_VECTOR_CPU_RESET_VECTOR);
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/* Select CPU complex clock source */
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writel(CCLK_PLLP_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
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/* Start the CPU0 clock and stop the CPU1 clock */
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reg = CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 | CPU_CMPLX_CPU0_CLK_STP_RUN |
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CPU_CMPLX_CPU1_CLK_STP_STOP;
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writel(reg, &clkrst->crc_clk_cpu_cmplx);
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/* Enable the CPU complex clock */
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reg = readl(&clkrst->crc_clk_out_enb[TEGRA_DEV_L]);
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reg |= CLK_ENB_CPU;
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writel(reg, &clkrst->crc_clk_out_enb[TEGRA_DEV_L]);
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/* Make sure the resets were held for at least 2 microseconds */
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reg = readl(TIMER_USEC_CNTR);
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while (readl(TIMER_USEC_CNTR) <= (reg + 2))
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;
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#ifdef DEBUG_RESET_CORESIGHT
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/*
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* De-assert CoreSight reset.
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* NOTE: We're leaving the CoreSight clock on the oscillator for
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* now. It will be restored to its original clock source
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* when the CPU-side restoration code runs.
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*/
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reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);
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reg &= ~SWR_CSITE_RST;
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writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);
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#endif
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/* Unlock the CPU CoreSight interfaces */
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reg = 0xC5ACCE55;
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writel(reg, CSITE_CPU_DBG0_LAR);
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writel(reg, CSITE_CPU_DBG1_LAR);
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/*
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* Sample the microsecond timestamp again. This is the time we must
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* use when returning from LP0 for PLL stabilization delays.
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*/
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reg = readl(TIMER_USEC_CNTR);
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writel(reg, &pmc->pmc_scratch1);
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pllx_base.word = 0;
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pllx_misc.word = 0;
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scratch3.word = readl(&pmc->pmc_scratch3);
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/* Get the OSC. For 19.2 MHz, use 19 to make the calculations easier */
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reg = (readl(TIMER_USEC_CFG) & USEC_CFG_DIVISOR_MASK) + 1;
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/*
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* According to the TRM, for 19.2MHz OSC, the USEC_DIVISOR is 0x5f, and
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* USEC_DIVIDEND is 0x04. So, if USEC_DIVISOR > 26, OSC is 19.2 MHz.
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*
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* reg is used to calculate the pllx freq, which is used to determine if
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* to set dccon or not.
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*/
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if (reg > 26)
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reg = 19;
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/* PLLX_BASE.PLLX_DIVM */
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if (scratch3.pllx_base_divm == reg)
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reg = 0;
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else
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reg = 1;
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/* PLLX_BASE.PLLX_DIVN */
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pllx_base.divn = scratch3.pllx_base_divn;
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reg = scratch3.pllx_base_divn << reg;
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/* PLLX_BASE.PLLX_DIVP */
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pllx_base.divp = scratch3.pllx_base_divp;
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reg = reg >> scratch3.pllx_base_divp;
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pllx_base.bypass = 1;
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/* PLLX_MISC_DCCON must be set for pllx frequency > 600 MHz. */
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if (reg > 600)
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pllx_misc.dccon = 1;
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/* PLLX_MISC_LFCON */
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pllx_misc.lfcon = scratch3.pllx_misc_lfcon;
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/* PLLX_MISC_CPCON */
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pllx_misc.cpcon = scratch3.pllx_misc_cpcon;
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writel(pllx_misc.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_misc);
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writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
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pllx_base.enable = 1;
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writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
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pllx_base.bypass = 0;
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writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
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writel(0, flow->halt_cpu_events);
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reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DERESET0;
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writel(reg, &clkrst->crc_cpu_cmplx_clr);
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reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE |
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PLLM_OUT1_RATIO_VAL_8;
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writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]);
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reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 |
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SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 |
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SCLK_SYS_STATE_IDLE;
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writel(reg, &clkrst->crc_sclk_brst_pol);
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/* avp_resume: no return after the write */
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reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);
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reg &= ~CPU_RST;
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writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
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/* avp_halt: */
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avp_halt:
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reg = EVENT_MODE_STOP | EVENT_JTAG;
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writel(reg, flow->halt_cop_events);
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goto avp_halt;
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do_reset:
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/*
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* Execution comes here if something goes wrong. The chip is reset and
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* a cold boot is performed.
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*/
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writel(SWR_TRIG_SYS_RST, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
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goto do_reset;
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}
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/*
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* wb_end() is a dummy function, and must be directly following wb_start(),
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* and is used to calculate the size of wb_start().
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*/
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void wb_end(void)
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{
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}
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