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c10806267d
Newer SoCs use same TV encoder unit. Split it out so it can be reused with new DM video driver. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org>
131 lines
4.6 KiB
C
131 lines
4.6 KiB
C
/*
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* Sunxi TV encoder register and constant defines
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*
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* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
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* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TVE_H
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#define _TVE_H
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enum tve_mode {
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tve_mode_vga,
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tve_mode_composite_pal,
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tve_mode_composite_ntsc,
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tve_mode_composite_pal_m,
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tve_mode_composite_pal_nc,
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};
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/*
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* This is based on the A10s User Manual, and the A10s only supports
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* composite video and not vga like the A10 / A20 does, still other
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* than the removed vga out capability the tvencoder seems to be the same.
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* "unknown#" registers are registers which are used in the A10 kernel code,
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* but not documented in the A10s User Manual.
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*/
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struct sunxi_tve_reg {
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u32 gctrl; /* 0x000 */
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u32 cfg0; /* 0x004 */
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u32 dac_cfg0; /* 0x008 */
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u32 filter; /* 0x00c */
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u32 chroma_freq; /* 0x010 */
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u32 porch_num; /* 0x014 */
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u32 unknown0; /* 0x018 */
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u32 line_num; /* 0x01c */
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u32 blank_black_level; /* 0x020 */
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u32 unknown1; /* 0x024, seems to be 1 byte per dac */
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u8 res0[0x08]; /* 0x028 */
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u32 auto_detect_en; /* 0x030 */
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u32 auto_detect_int_status; /* 0x034 */
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u32 auto_detect_status; /* 0x038 */
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u32 auto_detect_debounce; /* 0x03c */
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u32 csc_reg0; /* 0x040 */
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u32 csc_reg1; /* 0x044 */
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u32 csc_reg2; /* 0x048 */
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u32 csc_reg3; /* 0x04c */
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u8 res1[0xb0]; /* 0x050 */
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u32 color_burst; /* 0x100 */
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u32 vsync_num; /* 0x104 */
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u32 notch_freq; /* 0x108 */
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u32 cbr_level; /* 0x10c */
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u32 burst_phase; /* 0x110 */
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u32 burst_width; /* 0x114 */
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u32 unknown2; /* 0x118 */
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u32 sync_vbi_level; /* 0x11c */
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u32 white_level; /* 0x120 */
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u32 active_num; /* 0x124 */
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u32 chroma_bw_gain; /* 0x128 */
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u32 notch_width; /* 0x12c */
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u32 resync_num; /* 0x130 */
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u32 slave_para; /* 0x134 */
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u32 cfg1; /* 0x138 */
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u32 cfg2; /* 0x13c */
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};
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/*
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* TVE register constants.
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*/
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#define SUNXI_TVE_GCTRL_ENABLE (1 << 0)
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/*
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* Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed
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* dac from tve1. When using tve1 the mux value must be written to both tve0's
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* and tve1's gctrl reg.
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*/
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#define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac) (0xf << (((dac) + 1) * 4))
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#define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel) ((sel) << (((dac) + 1) * 4))
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#define SUNXI_TVE_CFG0_VGA 0x20000000
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#define SUNXI_TVE_CFG0_PAL 0x07030001
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#define SUNXI_TVE_CFG0_NTSC 0x07030000
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#define SUNXI_TVE_DAC_CFG0_VGA 0x403e1ac7
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#ifdef CONFIG_MACH_SUN5I
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#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x433f0009
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#else
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#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x403f0008
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#endif
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#define SUNXI_TVE_FILTER_COMPOSITE 0x00000120
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#define SUNXI_TVE_CHROMA_FREQ_PAL_M 0x21e6efe3
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#define SUNXI_TVE_CHROMA_FREQ_PAL_NC 0x21f69446
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#define SUNXI_TVE_PORCH_NUM_PAL 0x008a0018
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#define SUNXI_TVE_PORCH_NUM_NTSC 0x00760020
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#define SUNXI_TVE_LINE_NUM_PAL 0x00160271
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#define SUNXI_TVE_LINE_NUM_NTSC 0x0016020d
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#define SUNXI_TVE_BLANK_BLACK_LEVEL_PAL 0x00fc00fc
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#define SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC 0x00f0011a
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#define SUNXI_TVE_UNKNOWN1_VGA 0x00000000
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#define SUNXI_TVE_UNKNOWN1_COMPOSITE 0x18181818
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#define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac) (1 << ((dac) + 0))
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#define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac) (1 << ((dac) + 16))
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#define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac) (1 << ((dac) + 0))
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#define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac) ((dac) * 8)
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#define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac) (3 << ((dac) * 8))
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#define SUNXI_TVE_AUTO_DETECT_STATUS_NONE 0
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#define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED 1
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#define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND 3
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#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d) ((d) * 8)
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#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d) (0xf << ((d) * 8))
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#define SUNXI_TVE_CSC_REG0_ENABLE (1 << 31)
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#define SUNXI_TVE_CSC_REG0 0x08440832
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#define SUNXI_TVE_CSC_REG1 0x3b6dace1
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#define SUNXI_TVE_CSC_REG2 0x0e1d13dc
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#define SUNXI_TVE_CSC_REG3 0x00108080
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#define SUNXI_TVE_COLOR_BURST_PAL_M 0x00000000
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#define SUNXI_TVE_CBR_LEVEL_PAL 0x00002828
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#define SUNXI_TVE_CBR_LEVEL_NTSC 0x0000004f
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#define SUNXI_TVE_BURST_PHASE_NTSC 0x00000000
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#define SUNXI_TVE_BURST_WIDTH_COMPOSITE 0x0016447e
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#define SUNXI_TVE_UNKNOWN2_PAL 0x0000e0e0
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#define SUNXI_TVE_UNKNOWN2_NTSC 0x0000a0a0
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#define SUNXI_TVE_SYNC_VBI_LEVEL_NTSC 0x001000f0
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#define SUNXI_TVE_ACTIVE_NUM_COMPOSITE 0x000005a0
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#define SUNXI_TVE_CHROMA_BW_GAIN_COMP 0x00000002
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#define SUNXI_TVE_NOTCH_WIDTH_COMPOSITE 0x00000101
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#define SUNXI_TVE_RESYNC_NUM_PAL 0x800d000c
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#define SUNXI_TVE_RESYNC_NUM_NTSC 0x000e000c
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#define SUNXI_TVE_SLAVE_PARA_COMPOSITE 0x00000000
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void tvencoder_mode_set(struct sunxi_tve_reg * const tve, enum tve_mode mode);
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void tvencoder_enable(struct sunxi_tve_reg * const tve);
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#endif /* _TVE_H */
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