mirror of
https://github.com/AsahiLinux/u-boot
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7dfa44f72e
mux changes in board file to enable lpuart1 and macro define for lpuart1 used for mux changes in board configuation register 13 Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
335 lines
6.9 KiB
C
335 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <malloc.h>
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#include <errno.h>
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#include <fsl_ddr.h>
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#include <asm/io.h>
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#include <hwconfig.h>
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#include <fdt_support.h>
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#include <linux/libfdt.h>
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#include <env_internal.h>
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#include <asm/arch-fsl-layerscape/soc.h>
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#include <asm/arch-fsl-layerscape/fsl_icid.h>
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#include <i2c.h>
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#include <asm/arch/soc.h>
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#ifdef CONFIG_FSL_LS_PPA
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#include <asm/arch/ppa.h>
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#endif
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#include <fsl_immap.h>
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#include <netdev.h>
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#include <fdtdec.h>
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#include <miiphy.h>
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#include "../common/qixis.h"
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#include "../drivers/net/fsl_enetc.h"
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DECLARE_GLOBAL_DATA_PTR;
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int config_board_mux(void)
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{
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#ifndef CONFIG_LPUART
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#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
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u8 reg;
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reg = QIXIS_READ(brdcfg[13]);
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/* Field| Function
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* 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
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* I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
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* 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
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* I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
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*/
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reg &= ~(0xf0);
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reg |= 0xb0;
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QIXIS_WRITE(brdcfg[13], reg);
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reg = QIXIS_READ(brdcfg[15]);
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/* Field| Function
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* 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
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* CAN1 | 0= CAN #1 transceiver enabled
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* 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
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* CAN2 | 0= CAN #2 transceiver enabled
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*/
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reg &= ~(0xc0);
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QIXIS_WRITE(brdcfg[15], reg);
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#endif
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#endif
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return 0;
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}
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#ifdef CONFIG_LPUART
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u32 get_lpuart_clk(void)
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{
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return gd->bus_clk / CONFIG_SYS_FSL_LPUART_CLK_DIV;
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}
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#endif
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int board_init(void)
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{
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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#ifdef CONFIG_FSL_CAAM
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sec_init();
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#endif
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#ifdef CONFIG_FSL_LS_PPA
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ppa_init();
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#endif
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#ifndef CONFIG_SYS_EARLY_PCI_INIT
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pci_init();
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#endif
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#if defined(CONFIG_TARGET_LS1028ARDB)
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u8 val = I2C_MUX_CH_DEFAULT;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_MUX_PCA_ADDR_PRI, 0x0b, 1, &val, 1);
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#else
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struct udevice *dev;
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if (!i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev))
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dm_i2c_write(dev, 0x0b, &val, 1);
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#endif
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#endif
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#if defined(CONFIG_TARGET_LS1028ARDB)
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u8 reg;
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reg = QIXIS_READ(brdcfg[4]);
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/*
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* Field | Function
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* 3 | DisplayPort Power Enable (net DP_PWR_EN):
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* DPPWR | 0= DP_PWR is enabled.
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*/
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reg &= ~(DP_PWD_EN_DEFAULT_MASK);
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QIXIS_WRITE(brdcfg[4], reg);
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#endif
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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config_board_mux();
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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#ifdef CONFIG_LPUART
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u8 uart;
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#endif
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#ifdef CONFIG_SYS_I2C_EARLY_INIT
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i2c_early_init_f();
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#endif
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fsl_lsch3_early_init_f();
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#ifdef CONFIG_LPUART
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/*
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* Field| Function
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* --------------------------------------------------------------
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* 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
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* I2C3 | 11= Routes {SCL, SDA} to LPUART1 header as {SOUT, SIN}.
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* --------------------------------------------------------------
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* 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
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* I2C4 |11= Routes {SCL, SDA} to LPUART1 header as {CTS_B, RTS_B}.
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*/
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/* use lpuart0 as system console */
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uart = QIXIS_READ(brdcfg[13]);
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uart &= ~CFG_LPUART_MUX_MASK;
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uart |= CFG_LPUART_EN;
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QIXIS_WRITE(brdcfg[13], uart);
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#endif
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return 0;
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}
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void detail_board_ddr_info(void)
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{
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puts("\nDDR ");
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print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
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print_ddr_info(0);
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}
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int esdhc_status_fixup(void *blob, const char *compat)
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{
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void __iomem *dcfg_ccsr = (void __iomem *)DCFG_BASE;
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char esdhc1_path[] = "/soc/mmc@2140000";
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char esdhc2_path[] = "/soc/mmc@2150000";
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char dspi1_path[] = "/soc/spi@2100000";
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char dspi2_path[] = "/soc/spi@2110000";
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u32 mux_sdhc1, mux_sdhc2;
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u32 io = 0;
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/*
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* The PMUX IO-expander for mux select is used to control
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* the muxing of various onboard interfaces.
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*/
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io = in_le32(dcfg_ccsr + DCFG_RCWSR12);
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mux_sdhc1 = (io >> DCFG_RCWSR12_SDHC_SHIFT) & DCFG_RCWSR12_SDHC_MASK;
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/* Disable esdhc1/dspi1 if not selected. */
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if (mux_sdhc1 != 0)
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do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
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sizeof("disabled"), 1);
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if (mux_sdhc1 != 2)
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do_fixup_by_path(blob, dspi1_path, "status", "disabled",
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sizeof("disabled"), 1);
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io = in_le32(dcfg_ccsr + DCFG_RCWSR13);
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mux_sdhc2 = (io >> DCFG_RCWSR13_SDHC_SHIFT) & DCFG_RCWSR13_SDHC_MASK;
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/* Disable esdhc2/dspi2 if not selected. */
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if (mux_sdhc2 != 0)
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do_fixup_by_path(blob, esdhc2_path, "status", "disabled",
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sizeof("disabled"), 1);
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if (mux_sdhc2 != 2)
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do_fixup_by_path(blob, dspi2_path, "status", "disabled",
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sizeof("disabled"), 1);
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return 0;
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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u64 base[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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ft_cpu_setup(blob, bd);
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/* fixup DT for the two GPP DDR banks */
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base[0] = gd->bd->bi_dram[0].start;
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size[0] = gd->bd->bi_dram[0].size;
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base[1] = gd->bd->bi_dram[1].start;
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size[1] = gd->bd->bi_dram[1].size;
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#ifdef CONFIG_RESV_RAM
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/* reduce size if reserved memory is within this bank */
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if (gd->arch.resv_ram >= base[0] &&
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gd->arch.resv_ram < base[0] + size[0])
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size[0] = gd->arch.resv_ram - base[0];
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else if (gd->arch.resv_ram >= base[1] &&
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gd->arch.resv_ram < base[1] + size[1])
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size[1] = gd->arch.resv_ram - base[1];
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#endif
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fdt_fixup_memory_banks(blob, base, size, 2);
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fdt_fixup_icid(blob);
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#ifdef CONFIG_FSL_ENETC
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fdt_fixup_enetc_mac(blob);
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_FSL_QIXIS
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int checkboard(void)
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{
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#ifdef CONFIG_TFABOOT
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enum boot_src src = get_boot_src();
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#endif
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u8 sw;
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int clock;
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char *board;
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char buf[64] = {0};
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static const char *freq[6] = {"100.00", "125.00", "156.25",
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"161.13", "322.26", "100.00 SS"};
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cpu_name(buf);
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/* find the board details */
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sw = QIXIS_READ(id);
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switch (sw) {
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case 0x46:
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board = "QDS";
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break;
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case 0x47:
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board = "RDB";
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break;
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case 0x49:
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board = "HSSI";
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break;
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default:
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board = "unknown";
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break;
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}
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sw = QIXIS_READ(arch);
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printf("Board: %s-%s, Version: %c, boot from ",
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buf, board, (sw & 0xf) + 'A' - 1);
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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#ifdef CONFIG_TFABOOT
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if (src == BOOT_SOURCE_SD_MMC) {
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puts("SD\n");
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} else if (src == BOOT_SOURCE_SD_MMC2) {
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puts("eMMC\n");
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} else {
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#endif
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#ifdef CONFIG_SD_BOOT
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puts("SD\n");
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#elif defined(CONFIG_EMMC_BOOT)
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puts("eMMC\n");
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#else
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switch (sw) {
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case 0:
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case 4:
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printf("NOR\n");
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break;
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case 1:
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printf("NAND\n");
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break;
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default:
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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break;
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}
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#endif
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#ifdef CONFIG_TFABOOT
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}
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#endif
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printf("FPGA: v%d (%s)\n", QIXIS_READ(scver), board);
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puts("SERDES1 Reference : ");
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sw = QIXIS_READ(brdcfg[2]);
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#ifdef CONFIG_TARGET_LS1028ARDB
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clock = (sw >> 6) & 3;
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#else
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clock = (sw >> 4) & 0xf;
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#endif
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printf("Clock1 = %sMHz ", freq[clock]);
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#ifdef CONFIG_TARGET_LS1028ARDB
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clock = (sw >> 4) & 3;
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#else
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clock = sw & 0xf;
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#endif
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printf("Clock2 = %sMHz\n", freq[clock]);
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return 0;
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}
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#endif
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