mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
1cf6825a68
There is no need to keep a separate coreboot_fb.dtsi since now we have a generic coreboot payload dts. While we are here, this also remove the out-of-date description in the documentation regarding to coreboot framebuffer driver with U-Boot loaded as a payload from coreboot. As the testing result with QEMU 2.5.0 shows, the driver just works like a charm. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
494 lines
9.8 KiB
Text
494 lines
9.8 KiB
Text
/dts-v1/;
|
|
|
|
#include <dt-bindings/gpio/x86-gpio.h>
|
|
|
|
/include/ "skeleton.dtsi"
|
|
/include/ "keyboard.dtsi"
|
|
/include/ "serial.dtsi"
|
|
/include/ "reset.dtsi"
|
|
/include/ "rtc.dtsi"
|
|
/include/ "tsc_timer.dtsi"
|
|
|
|
/ {
|
|
model = "Google Link";
|
|
compatible = "google,link", "intel,celeron-ivybridge";
|
|
|
|
aliases {
|
|
spi0 = &spi;
|
|
usb0 = &usb_0;
|
|
usb1 = &usb_1;
|
|
};
|
|
|
|
config {
|
|
silent_console = <0>;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "intel,core-gen3";
|
|
reg = <0>;
|
|
intel,apic-id = <0>;
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "intel,core-gen3";
|
|
reg = <1>;
|
|
intel,apic-id = <1>;
|
|
};
|
|
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "intel,core-gen3";
|
|
reg = <2>;
|
|
intel,apic-id = <2>;
|
|
};
|
|
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "intel,core-gen3";
|
|
reg = <3>;
|
|
intel,apic-id = <3>;
|
|
};
|
|
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "/serial";
|
|
};
|
|
|
|
keyboard {
|
|
intel,duplicate-por;
|
|
};
|
|
|
|
pch_pinctrl {
|
|
compatible = "intel,x86-pinctrl";
|
|
u-boot,dm-pre-reloc;
|
|
reg = <0 0>;
|
|
|
|
gpio_a0 {
|
|
gpio-offset = <0 0>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
};
|
|
|
|
gpio_a1 {
|
|
gpio-offset = <0>;
|
|
mode-gpio;
|
|
direction = <PIN_OUTPUT>;
|
|
output-value = <1>;
|
|
};
|
|
|
|
gpio_a3 {
|
|
gpio-offset = <0 3>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
};
|
|
|
|
gpio_a5 {
|
|
gpio-offset = <0 5>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
};
|
|
|
|
gpio_a6 {
|
|
gpio-offset = <0 6>;
|
|
mode-gpio;
|
|
direction = <PIN_OUTPUT>;
|
|
output-value = <1>;
|
|
};
|
|
|
|
gpio_a7 {
|
|
gpio-offset = <0 7>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
invert;
|
|
};
|
|
|
|
gpio_a8 {
|
|
gpio-offset = <0 8>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
invert;
|
|
};
|
|
|
|
gpio_a9 {
|
|
gpio-offset = <0 9>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
};
|
|
|
|
gpio_a10 {
|
|
u-boot,dm-pre-reloc;
|
|
gpio-offset = <0 10>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
};
|
|
|
|
gpio_a11 {
|
|
gpio-offset = <0 11>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
};
|
|
|
|
gpio_a12 {
|
|
gpio-offset = <0 12>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
invert;
|
|
};
|
|
|
|
gpio_a14 {
|
|
gpio-offset = <0 14>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
invert;
|
|
};
|
|
|
|
gpio_a15 {
|
|
gpio-offset = <0 15>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
invert;
|
|
};
|
|
|
|
gpio_a21 {
|
|
gpio-offset = <0 21>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
};
|
|
|
|
gpio_a24 {
|
|
gpio-offset = <0 24>;
|
|
mode-gpio;
|
|
output-value = <0>;
|
|
direction = <PIN_OUTPUT>;
|
|
};
|
|
|
|
gpio_a28 {
|
|
gpio-offset = <0 28>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
};
|
|
|
|
gpio_b4 {
|
|
gpio-offset = <0x30 4>;
|
|
mode-gpio;
|
|
direction = <PIN_OUTPUT>;
|
|
output-value = <1>;
|
|
};
|
|
|
|
gpio_b9 {
|
|
u-boot,dm-pre-reloc;
|
|
gpio-offset = <0x30 9>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
};
|
|
|
|
gpio_b10 {
|
|
u-boot,dm-pre-reloc;
|
|
gpio-offset = <0x30 10>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
};
|
|
|
|
gpio_b11 {
|
|
u-boot,dm-pre-reloc;
|
|
gpio-offset = <0x30 11>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
};
|
|
|
|
gpio_b25 {
|
|
gpio-offset = <0x30 25>;
|
|
mode-gpio;
|
|
direction = <PIN_INPUT>;
|
|
};
|
|
|
|
gpio_b28 {
|
|
gpio-offset = <0x30 28>;
|
|
mode-gpio;
|
|
direction = <PIN_OUTPUT>;
|
|
output-value = <1>;
|
|
};
|
|
|
|
};
|
|
|
|
pci {
|
|
compatible = "pci-x86";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
u-boot,dm-pre-reloc;
|
|
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
|
|
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
|
|
0x01000000 0x0 0x1000 0x1000 0 0xefff>;
|
|
|
|
northbridge@0,0 {
|
|
reg = <0x00000000 0 0 0 0>;
|
|
u-boot,dm-pre-reloc;
|
|
compatible = "intel,bd82x6x-northbridge";
|
|
board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
|
|
<&gpio_b 11 0>, <&gpio_a 10 0>;
|
|
spd {
|
|
u-boot,dm-pre-reloc;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
elpida_4Gb_1600_x16 {
|
|
u-boot,dm-pre-reloc;
|
|
reg = <0>;
|
|
data = [92 10 0b 03 04 19 02 02
|
|
03 52 01 08 0a 00 fe 00
|
|
69 78 69 3c 69 11 18 81
|
|
20 08 3c 3c 01 40 83 81
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 0f 11 42 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 02 fe 00
|
|
11 52 00 00 00 07 7f 37
|
|
45 42 4a 32 30 55 47 36
|
|
45 42 55 30 2d 47 4e 2d
|
|
46 20 30 20 02 fe 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00];
|
|
};
|
|
samsung_4Gb_1600_1.35v_x16 {
|
|
u-boot,dm-pre-reloc;
|
|
reg = <1>;
|
|
data = [92 11 0b 03 04 19 02 02
|
|
03 11 01 08 0a 00 fe 00
|
|
69 78 69 3c 69 11 18 81
|
|
f0 0a 3c 3c 01 40 83 01
|
|
00 80 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 0f 11 02 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 80 ce 01
|
|
00 00 00 00 00 00 6a 04
|
|
4d 34 37 31 42 35 36 37
|
|
34 42 48 30 2d 59 4b 30
|
|
20 20 00 00 80 ce 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00];
|
|
};
|
|
micron_4Gb_1600_1.35v_x16 {
|
|
reg = <2>;
|
|
data = [92 11 0b 03 04 19 02 02
|
|
03 11 01 08 0a 00 fe 00
|
|
69 78 69 3c 69 11 18 81
|
|
20 08 3c 3c 01 40 83 05
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 0f 01 02 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 80 2c 00
|
|
00 00 00 00 00 00 ad 75
|
|
34 4b 54 46 32 35 36 36
|
|
34 48 5a 2d 31 47 36 45
|
|
31 20 45 31 80 2c 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
00 00 00 00 00 00 00 00
|
|
ff ff ff ff ff ff ff ff
|
|
ff ff ff ff ff ff ff ff
|
|
ff ff ff ff ff ff ff ff
|
|
ff ff ff ff ff ff ff ff
|
|
ff ff ff ff ff ff ff ff
|
|
ff ff ff ff ff ff ff ff
|
|
ff ff ff ff ff ff ff ff
|
|
ff ff ff ff ff ff ff ff
|
|
ff ff ff ff ff ff ff ff
|
|
ff ff ff ff ff ff ff ff];
|
|
};
|
|
};
|
|
};
|
|
|
|
gma@2,0 {
|
|
reg = <0x00001000 0 0 0 0>;
|
|
compatible = "intel,gma";
|
|
intel,dp_hotplug = <0 0 0x06>;
|
|
intel,panel-port-select = <1>;
|
|
intel,panel-power-cycle-delay = <6>;
|
|
intel,panel-power-up-delay = <2000>;
|
|
intel,panel-power-down-delay = <500>;
|
|
intel,panel-power-backlight-on-delay = <2000>;
|
|
intel,panel-power-backlight-off-delay = <2000>;
|
|
intel,cpu-backlight = <0x00000200>;
|
|
intel,pch-backlight = <0x04000000>;
|
|
};
|
|
|
|
me@16,0 {
|
|
reg = <0x0000b000 0 0 0 0>;
|
|
compatible = "intel,me";
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
usb_1: usb@1a,0 {
|
|
reg = <0x0000d000 0 0 0 0>;
|
|
compatible = "ehci-pci";
|
|
};
|
|
|
|
usb_0: usb@1d,0 {
|
|
reg = <0x0000e800 0 0 0 0>;
|
|
compatible = "ehci-pci";
|
|
};
|
|
|
|
pch@1f,0 {
|
|
reg = <0x0000f800 0 0 0 0>;
|
|
compatible = "intel,bd82x6x", "intel,pch9";
|
|
u-boot,dm-pre-reloc;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
|
|
0x80 0x80 0x80 0x80>;
|
|
intel,gpi-routing = <0 0 0 0 0 0 0 2
|
|
1 0 0 0 0 0 0 0>;
|
|
/* Enable EC SMI source */
|
|
intel,alt-gp-smi-enable = <0x0100>;
|
|
|
|
spi: spi {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "intel,ich9-spi";
|
|
u-boot,dm-pre-reloc;
|
|
spi-flash@0 {
|
|
#size-cells = <1>;
|
|
#address-cells = <1>;
|
|
u-boot,dm-pre-reloc;
|
|
reg = <0>;
|
|
compatible = "winbond,w25q64",
|
|
"spi-flash";
|
|
memory-map = <0xff800000 0x00800000>;
|
|
rw-mrc-cache {
|
|
label = "rw-mrc-cache";
|
|
reg = <0x003e0000 0x00010000>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpio_a: gpioa {
|
|
compatible = "intel,ich6-gpio";
|
|
u-boot,dm-pre-reloc;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
reg = <0 0x10>;
|
|
bank-name = "A";
|
|
};
|
|
|
|
gpio_b: gpiob {
|
|
compatible = "intel,ich6-gpio";
|
|
u-boot,dm-pre-reloc;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
reg = <0x30 0x10>;
|
|
bank-name = "B";
|
|
};
|
|
|
|
gpio_c: gpioc {
|
|
compatible = "intel,ich6-gpio";
|
|
u-boot,dm-pre-reloc;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
reg = <0x40 0x10>;
|
|
bank-name = "C";
|
|
};
|
|
|
|
lpc {
|
|
compatible = "intel,bd82x6x-lpc";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
u-boot,dm-pre-reloc;
|
|
intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
|
|
cros-ec@200 {
|
|
compatible = "google,cros-ec";
|
|
reg = <0x204 1 0x200 1 0x880 0x80>;
|
|
|
|
/*
|
|
* Describes the flash memory within
|
|
* the EC
|
|
*/
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
flash@8000000 {
|
|
reg = <0x08000000 0x20000>;
|
|
erase-value = <0xff>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
sata@1f,2 {
|
|
compatible = "intel,pantherpoint-ahci";
|
|
reg = <0x0000fa00 0 0 0 0>;
|
|
u-boot,dm-pre-reloc;
|
|
intel,sata-mode = "ahci";
|
|
intel,sata-port-map = <1>;
|
|
intel,sata-port0-gen3-tx = <0x00880a7f>;
|
|
};
|
|
|
|
smbus: smbus@1f,3 {
|
|
compatible = "intel,ich-i2c";
|
|
reg = <0x0000fb00 0 0 0 0>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
|
|
tpm {
|
|
reg = <0xfed40000 0x5000>;
|
|
compatible = "infineon,slb9635lpc";
|
|
};
|
|
|
|
microcode {
|
|
u-boot,dm-pre-reloc;
|
|
update@0 {
|
|
u-boot,dm-pre-reloc;
|
|
#include "microcode/m12306a9_0000001b.dtsi"
|
|
};
|
|
};
|
|
|
|
};
|