mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-29 10:52:09 +00:00
dcbc95c23c
Add the needed bus mappings for the two main RTI memory ranges and the required device tree nodes in the main domain. Same as kernel commit 6dd8457dc20693e2ba9054c171499b22664fd4e7 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
108 lines
3.8 KiB
Text
108 lines
3.8 KiB
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Device Tree Source for AM642 SoC Family
|
|
*
|
|
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
|
*/
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/pinctrl/k3.h>
|
|
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
|
|
|
/ {
|
|
model = "Texas Instruments K3 AM642 SoC";
|
|
compatible = "ti,am642";
|
|
interrupt-parent = <&gic500>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
aliases {
|
|
serial0 = &mcu_uart0;
|
|
serial1 = &mcu_uart1;
|
|
serial2 = &main_uart0;
|
|
serial3 = &main_uart1;
|
|
serial4 = &main_uart2;
|
|
serial5 = &main_uart3;
|
|
serial6 = &main_uart4;
|
|
serial7 = &main_uart5;
|
|
serial8 = &main_uart6;
|
|
ethernet0 = &cpsw_port1;
|
|
ethernet1 = &cpsw_port2;
|
|
};
|
|
|
|
chosen { };
|
|
|
|
firmware {
|
|
optee {
|
|
compatible = "linaro,optee-tz";
|
|
method = "smc";
|
|
};
|
|
|
|
psci: psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
};
|
|
|
|
a53_timer0: timer-cl0-cpu0 {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
|
};
|
|
|
|
pmu: pmu {
|
|
compatible = "arm,cortex-a53-pmu";
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
cbass_main: bus@f4000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
|
|
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
|
|
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
|
|
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
|
|
<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
|
|
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
|
|
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
|
|
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
|
|
<0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
|
|
<0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
|
|
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
|
|
<0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
|
|
<0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
|
|
<0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
|
|
<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
|
|
<0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
|
|
<0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
|
|
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
|
|
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
|
|
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
|
|
<0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
|
|
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
|
|
<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
|
|
<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
|
|
<0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
|
|
<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
|
|
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
|
|
|
|
/* MCU Domain Range */
|
|
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
|
|
|
|
cbass_mcu: bus@4000000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
|
|
};
|
|
};
|
|
};
|
|
|
|
/* Now include the peripherals for each bus segments */
|
|
#include "k3-am64-main.dtsi"
|
|
#include "k3-am64-mcu.dtsi"
|