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https://github.com/AsahiLinux/u-boot
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20a58ac0d8
Even though existing implementation works fine in preparation to submission of ARCv2 architecture we need this change. In case of ARCv2 interrupt vector table consists of just addresses of corresponding handlers. And if those addresses will be in .text section then assembler will encode them as everything in .text section as middle-endian and then on real execution CPU will read swapped addresses and will jump into the wild. Once introduced new section is situated so .text section remains the first which allows us to use common linker option for linking everything to a specified CONFIG_SYS_TEXT_BASE. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
254 lines
5.1 KiB
ArmAsm
254 lines
5.1 KiB
ArmAsm
/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/arcregs.h>
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/*
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* Note on the LD/ST addressing modes with address register write-back
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*
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* LD.a same as LD.aw
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*
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* LD.a reg1, [reg2, x] => Pre Incr
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* Eff Addr for load = [reg2 + x]
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*
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* LD.ab reg1, [reg2, x] => Post Incr
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* Eff Addr for load = [reg2]
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*/
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.macro PUSH reg
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st.a \reg, [%sp, -4]
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.endm
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.macro PUSHAX aux
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lr %r9, [\aux]
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PUSH %r9
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.endm
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.macro SAVE_R1_TO_R24
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PUSH %r1
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PUSH %r2
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PUSH %r3
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PUSH %r4
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PUSH %r5
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PUSH %r6
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PUSH %r7
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PUSH %r8
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PUSH %r9
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PUSH %r10
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PUSH %r11
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PUSH %r12
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PUSH %r13
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PUSH %r14
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PUSH %r15
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PUSH %r16
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PUSH %r17
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PUSH %r18
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PUSH %r19
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PUSH %r20
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PUSH %r21
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PUSH %r22
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PUSH %r23
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PUSH %r24
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.endm
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.macro SAVE_ALL_SYS
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/* saving %r0 to reg->r0 in advance since we read %ecr into it */
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st %r0, [%sp, -8]
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lr %r0, [%ecr] /* all stack addressing is manual so far */
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st %r0, [%sp]
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st %sp, [%sp, -4]
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/* now move %sp to reg->r0 position so we can do "push" automatically */
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sub %sp, %sp, 8
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SAVE_R1_TO_R24
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PUSH %r25
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PUSH %gp
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PUSH %fp
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PUSH %blink
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PUSHAX %eret
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PUSHAX %erstatus
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PUSH %lp_count
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PUSHAX %lp_end
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PUSHAX %lp_start
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PUSHAX %erbta
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.endm
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.macro SAVE_EXCEPTION_SOURCE
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#ifdef CONFIG_MMU
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/* If MMU exists exception faulting address is loaded in EFA reg */
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lr %r0, [%efa]
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#else
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/* Otherwise in ERET (exception return) reg */
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lr %r0, [%eret]
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#endif
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.endm
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.section .ivt, "ax",@progbits
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.align 4
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_ivt:
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/* Critical system events */
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j _start /* 0 - 0x000 */
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j memory_error /* 1 - 0x008 */
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j instruction_error /* 2 - 0x010 */
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/* Device interrupts */
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.rept 29
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j interrupt_handler /* 3:31 - 0x018:0xF8 */
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.endr
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/* Exceptions */
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j EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */
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j EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */
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j EV_TLBMissD /* 0x110, Data TLB miss (0x22) */
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j EV_TLBProtV /* 0x118, Protection Violation (0x23)
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or Misaligned Access */
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j EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */
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j EV_Trap /* 0x128, Trap exception (0x25) */
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j EV_Extension /* 0x130, Extn Intruction Excp (0x26) */
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.text
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.globl _start
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_start:
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/* Setup interrupt vector base that matches "__text_start" */
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sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
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/* Setup stack pointer */
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mov %sp, CONFIG_SYS_INIT_SP_ADDR
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mov %fp, %sp
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/* Clear bss */
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mov %r0, __bss_start
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mov %r1, __bss_end
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clear_bss:
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st.ab 0, [%r0, 4]
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brlt %r0, %r1, clear_bss
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/* Zero the one and only argument of "board_init_f" */
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mov_s %r0, 0
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j board_init_f
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memory_error:
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SAVE_ALL_SYS
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SAVE_EXCEPTION_SOURCE
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mov %r1, %sp
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j do_memory_error
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instruction_error:
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SAVE_ALL_SYS
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SAVE_EXCEPTION_SOURCE
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mov %r1, %sp
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j do_instruction_error
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interrupt_handler:
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/* Todo - save and restore CPU context when interrupts will be in use */
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bl do_interrupt_handler
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rtie
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EV_MachineCheck:
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SAVE_ALL_SYS
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SAVE_EXCEPTION_SOURCE
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mov %r1, %sp
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j do_machine_check_fault
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EV_TLBMissI:
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SAVE_ALL_SYS
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mov %r0, %sp
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j do_itlb_miss
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EV_TLBMissD:
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SAVE_ALL_SYS
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mov %r0, %sp
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j do_dtlb_miss
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EV_TLBProtV:
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SAVE_ALL_SYS
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SAVE_EXCEPTION_SOURCE
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mov %r1, %sp
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j do_tlb_prot_violation
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EV_PrivilegeV:
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SAVE_ALL_SYS
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mov %r0, %sp
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j do_privilege_violation
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EV_Trap:
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SAVE_ALL_SYS
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mov %r0, %sp
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j do_trap
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EV_Extension:
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SAVE_ALL_SYS
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mov %r0, %sp
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j do_extension
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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* r0 = start_addr_sp
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* r1 = new__gd
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* r2 = relocaddr
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*/
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.align 4
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.globl relocate_code
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relocate_code:
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/*
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* r0-r12 might be clobbered by C functions
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* so we use r13-r16 for storage here
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*/
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mov %r13, %r0 /* save addr_sp */
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mov %r14, %r1 /* save addr of gd */
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mov %r15, %r2 /* save addr of destination */
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mov %r16, %r2 /* %r9 - relocation offset */
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sub %r16, %r16, __image_copy_start
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/* Set up the stack */
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stack_setup:
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mov %sp, %r13
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mov %fp, %sp
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/* Check if monitor is loaded right in place for relocation */
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mov %r0, __image_copy_start
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cmp %r0, %r15 /* skip relocation if code loaded */
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bz do_board_init_r /* in target location already */
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/* Copy data (__image_copy_start - __image_copy_end) to new location */
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mov %r1, %r15
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mov %r2, __image_copy_end
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sub %r2, %r2, %r0 /* r3 <- amount of bytes to copy */
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asr %r2, %r2, 2 /* r3 <- amount of words to copy */
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mov %lp_count, %r2
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lp copy_end
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ld.ab %r2,[%r0,4]
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st.ab %r2,[%r1,4]
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copy_end:
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/* Fix relocations related issues */
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bl do_elf_reloc_fixups
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#ifndef CONFIG_SYS_ICACHE_OFF
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bl invalidate_icache_all
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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bl flush_dcache_all
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#endif
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/* Update position of intterupt vector table */
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lr %r0, [ARC_AUX_INTR_VEC_BASE] /* Read current position */
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add %r0, %r0, %r16 /* Update address */
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sr %r0, [ARC_AUX_INTR_VEC_BASE] /* Write new position */
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do_board_init_r:
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/* Prepare for exection of "board_init_r" in relocated monitor */
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mov %r2, board_init_r /* old address of "board_init_r()" */
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add %r2, %r2, %r16 /* new address of "board_init_r()" */
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mov %r0, %r14 /* 1-st parameter: gd_t */
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mov %r1, %r15 /* 2-nd parameter: dest_addr */
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j [%r2]
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