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790f7719e2
Tegra210 starts its drive group registers at a different offset from the APB MISC register block that other SoCs. Update the code to handle this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
239 lines
4.4 KiB
C
239 lines
4.4 KiB
C
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA20_PINMUX_H_
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#define _TEGRA20_PINMUX_H_
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/*
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* Pin groups which we adjust. There are three basic attributes of each pin
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* group which use this enum:
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*
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* - function
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* - pullup / pulldown
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* - tristate or normal
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*/
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enum pmux_pingrp {
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/* APB_MISC_PP_TRISTATE_REG_A_0 */
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PMUX_PINGRP_ATA,
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PMUX_PINGRP_ATB,
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PMUX_PINGRP_ATC,
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PMUX_PINGRP_ATD,
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PMUX_PINGRP_CDEV1,
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PMUX_PINGRP_CDEV2,
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PMUX_PINGRP_CSUS,
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PMUX_PINGRP_DAP1,
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PMUX_PINGRP_DAP2,
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PMUX_PINGRP_DAP3,
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PMUX_PINGRP_DAP4,
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PMUX_PINGRP_DTA,
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PMUX_PINGRP_DTB,
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PMUX_PINGRP_DTC,
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PMUX_PINGRP_DTD,
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PMUX_PINGRP_DTE,
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PMUX_PINGRP_GPU,
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PMUX_PINGRP_GPV,
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PMUX_PINGRP_I2CP,
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PMUX_PINGRP_IRTX,
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PMUX_PINGRP_IRRX,
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PMUX_PINGRP_KBCB,
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PMUX_PINGRP_KBCA,
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PMUX_PINGRP_PMC,
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PMUX_PINGRP_PTA,
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PMUX_PINGRP_RM,
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PMUX_PINGRP_KBCE,
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PMUX_PINGRP_KBCF,
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PMUX_PINGRP_GMA,
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PMUX_PINGRP_GMC,
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PMUX_PINGRP_SDIO1,
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PMUX_PINGRP_OWC,
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/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
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PMUX_PINGRP_GME,
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PMUX_PINGRP_SDC,
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PMUX_PINGRP_SDD,
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PMUX_PINGRP_RESERVED0,
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PMUX_PINGRP_SLXA,
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PMUX_PINGRP_SLXC,
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PMUX_PINGRP_SLXD,
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PMUX_PINGRP_SLXK,
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PMUX_PINGRP_SPDI,
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PMUX_PINGRP_SPDO,
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PMUX_PINGRP_SPIA,
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PMUX_PINGRP_SPIB,
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PMUX_PINGRP_SPIC,
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PMUX_PINGRP_SPID,
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PMUX_PINGRP_SPIE,
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PMUX_PINGRP_SPIF,
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PMUX_PINGRP_SPIG,
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PMUX_PINGRP_SPIH,
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PMUX_PINGRP_UAA,
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PMUX_PINGRP_UAB,
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PMUX_PINGRP_UAC,
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PMUX_PINGRP_UAD,
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PMUX_PINGRP_UCA,
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PMUX_PINGRP_UCB,
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PMUX_PINGRP_RESERVED1,
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PMUX_PINGRP_ATE,
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PMUX_PINGRP_KBCC,
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PMUX_PINGRP_RESERVED2,
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PMUX_PINGRP_RESERVED3,
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PMUX_PINGRP_GMB,
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PMUX_PINGRP_GMD,
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PMUX_PINGRP_DDC,
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/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
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PMUX_PINGRP_LD0,
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PMUX_PINGRP_LD1,
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PMUX_PINGRP_LD2,
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PMUX_PINGRP_LD3,
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PMUX_PINGRP_LD4,
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PMUX_PINGRP_LD5,
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PMUX_PINGRP_LD6,
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PMUX_PINGRP_LD7,
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PMUX_PINGRP_LD8,
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PMUX_PINGRP_LD9,
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PMUX_PINGRP_LD10,
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PMUX_PINGRP_LD11,
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PMUX_PINGRP_LD12,
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PMUX_PINGRP_LD13,
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PMUX_PINGRP_LD14,
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PMUX_PINGRP_LD15,
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PMUX_PINGRP_LD16,
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PMUX_PINGRP_LD17,
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PMUX_PINGRP_LHP0,
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PMUX_PINGRP_LHP1,
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PMUX_PINGRP_LHP2,
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PMUX_PINGRP_LVP0,
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PMUX_PINGRP_LVP1,
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PMUX_PINGRP_HDINT,
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PMUX_PINGRP_LM0,
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PMUX_PINGRP_LM1,
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PMUX_PINGRP_LVS,
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PMUX_PINGRP_LSC0,
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PMUX_PINGRP_LSC1,
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PMUX_PINGRP_LSCK,
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PMUX_PINGRP_LDC,
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PMUX_PINGRP_LCSN,
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/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
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PMUX_PINGRP_LSPI,
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PMUX_PINGRP_LSDA,
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PMUX_PINGRP_LSDI,
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PMUX_PINGRP_LPW0,
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PMUX_PINGRP_LPW1,
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PMUX_PINGRP_LPW2,
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PMUX_PINGRP_LDI,
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PMUX_PINGRP_LHS,
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PMUX_PINGRP_LPP,
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PMUX_PINGRP_RESERVED4,
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PMUX_PINGRP_KBCD,
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PMUX_PINGRP_GPU7,
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PMUX_PINGRP_DTF,
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PMUX_PINGRP_UDA,
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PMUX_PINGRP_CRTP,
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PMUX_PINGRP_SDB,
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/* these pin groups only have pullup and pull down control */
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PMUX_PINGRP_CK32,
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PMUX_PINGRP_DDRC,
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PMUX_PINGRP_PMCA,
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PMUX_PINGRP_PMCB,
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PMUX_PINGRP_PMCC,
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PMUX_PINGRP_PMCD,
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PMUX_PINGRP_PMCE,
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PMUX_PINGRP_XM2C,
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PMUX_PINGRP_XM2D,
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PMUX_PINGRP_COUNT,
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};
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/*
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* Functions which can be assigned to each of the pin groups. The values here
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* bear no relation to the values programmed into pinmux registers and are
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* purely a convenience. The translation is done through a table search.
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*/
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enum pmux_func {
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PMUX_FUNC_DEFAULT,
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PMUX_FUNC_AHB_CLK,
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PMUX_FUNC_APB_CLK,
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PMUX_FUNC_AUDIO_SYNC,
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PMUX_FUNC_CRT,
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PMUX_FUNC_DAP1,
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PMUX_FUNC_DAP2,
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PMUX_FUNC_DAP3,
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PMUX_FUNC_DAP4,
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PMUX_FUNC_DAP5,
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PMUX_FUNC_DISPA,
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PMUX_FUNC_DISPB,
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PMUX_FUNC_EMC_TEST0_DLL,
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PMUX_FUNC_EMC_TEST1_DLL,
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PMUX_FUNC_GMI,
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PMUX_FUNC_GMI_INT,
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PMUX_FUNC_HDMI,
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PMUX_FUNC_I2C,
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PMUX_FUNC_I2C2,
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PMUX_FUNC_I2C3,
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PMUX_FUNC_IDE,
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PMUX_FUNC_KBC,
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PMUX_FUNC_MIO,
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PMUX_FUNC_MIPI_HS,
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PMUX_FUNC_NAND,
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PMUX_FUNC_OSC,
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PMUX_FUNC_OWR,
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PMUX_FUNC_PCIE,
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PMUX_FUNC_PLLA_OUT,
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PMUX_FUNC_PLLC_OUT1,
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PMUX_FUNC_PLLM_OUT1,
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PMUX_FUNC_PLLP_OUT2,
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PMUX_FUNC_PLLP_OUT3,
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PMUX_FUNC_PLLP_OUT4,
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PMUX_FUNC_PWM,
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PMUX_FUNC_PWR_INTR,
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PMUX_FUNC_PWR_ON,
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PMUX_FUNC_RTCK,
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PMUX_FUNC_SDIO1,
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PMUX_FUNC_SDIO2,
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PMUX_FUNC_SDIO3,
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PMUX_FUNC_SDIO4,
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PMUX_FUNC_SFLASH,
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PMUX_FUNC_SPDIF,
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PMUX_FUNC_SPI1,
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PMUX_FUNC_SPI2,
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PMUX_FUNC_SPI2_ALT,
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PMUX_FUNC_SPI3,
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PMUX_FUNC_SPI4,
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PMUX_FUNC_TRACE,
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PMUX_FUNC_TWC,
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PMUX_FUNC_UARTA,
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PMUX_FUNC_UARTB,
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PMUX_FUNC_UARTC,
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PMUX_FUNC_UARTD,
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PMUX_FUNC_UARTE,
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PMUX_FUNC_ULPI,
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PMUX_FUNC_VI,
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PMUX_FUNC_VI_SENSOR_CLK,
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PMUX_FUNC_XIO,
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PMUX_FUNC_RSVD1,
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PMUX_FUNC_RSVD2,
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PMUX_FUNC_RSVD3,
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PMUX_FUNC_RSVD4,
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PMUX_FUNC_COUNT,
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};
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#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
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#include <asm/arch-tegra/pinmux.h>
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#endif /* _TEGRA20_PINMUX_H_ */
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