mirror of
https://github.com/AsahiLinux/u-boot
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e7afb73b50
Commit 345b77ba removed some nand_spl boards but
it missed to delete linker scripts.
These linker scripts are not used now.
And one more fix:
amcc/acadia does not support nand_spl anymore, so remove
#if !defined(CONFIG_NAND_U_BOOT) ... #endif
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
101 lines
2.5 KiB
C
101 lines
2.5 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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extern void board_pll_init_f(void);
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static void acadia_gpio_init(void)
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{
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/*
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* GPIO0 setup (select GPIO or alternate function)
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*/
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out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
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out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
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out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
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out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
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out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
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out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
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out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
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/*
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* Ultra (405EZ) was nice enough to add another GPIO controller
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*/
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out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH); /* output select */
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out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL);
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out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H); /* input select */
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out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L);
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out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH); /* three-state select */
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out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL);
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out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR); /* enable output driver for outputs */
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}
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int board_early_init_f(void)
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{
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unsigned int reg;
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/* don't reinit PLL when booting via I2C bootstrap option */
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mfsdr(SDR0_PINSTP, reg);
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if (reg != 0xf0000000)
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board_pll_init_f();
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acadia_gpio_init();
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/* Configure 405EZ for NAND usage */
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mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
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mfsdr(SDR0_ULTRA0, reg);
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reg &= ~SDR_ULTRA0_CSN_MASK;
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reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
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SDR_ULTRA0_NDGPIOBP |
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SDR_ULTRA0_EBCRDYEN |
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SDR_ULTRA0_NFSRSTEN;
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mtsdr(SDR0_ULTRA0, reg);
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/* USB Host core needs this bit set */
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mfsdr(SDR0_ULTRA1, reg);
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mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr(UIC0ER, 0x00000000); /* disable all ints */
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mtdcr(UIC0CR, 0x00000010);
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mtdcr(UIC0PR, 0xFE7FFFF0); /* set int polarities */
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mtdcr(UIC0TR, 0x00000010); /* set int trigger levels */
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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return 0;
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}
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int misc_init_f(void)
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{
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/* Set EPLD to take PHY out of reset */
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out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00);
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udelay(100000);
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return 0;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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u8 rev;
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rev = in8(CONFIG_SYS_CPLD_BASE + 0);
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printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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return (0);
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}
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