mirror of
https://github.com/AsahiLinux/u-boot
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7bfe0da4d2
Since BayTrail, Intel starts to use new GPIO IPs in their chipset. This adds the GPIO ASL, so that OS can load corresponding drivers for it. On Linux, this is BayTrail pinctrl driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
95 lines
1.5 KiB
Text
95 lines
1.5 KiB
Text
/*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* SouthCluster GPIO */
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Device (GPSC)
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{
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Name(_HID, "INT33FC")
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Name(_CID, "INT33FC")
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Name(_UID, 1)
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Name(RBUF, ResourceTemplate()
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{
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Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
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Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
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{
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GPIO_SC_IRQ
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}
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})
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Method(_CRS)
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{
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CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
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Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
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Return (^RBUF)
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}
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Method(_STA)
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{
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Return (STA_VISIBLE)
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}
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}
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/* NorthCluster GPIO */
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Device (GPNC)
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{
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Name(_HID, "INT33FC")
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Name(_CID, "INT33FC")
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Name(_UID, 2)
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Name(RBUF, ResourceTemplate()
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{
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Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
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Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
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{
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GPIO_NC_IRQ
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}
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})
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Method(_CRS)
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{
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CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
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Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
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Return (^RBUF)
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}
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Method(_STA)
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{
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Return (STA_VISIBLE)
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}
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}
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/* SUS GPIO */
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Device (GPSS)
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{
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Name(_HID, "INT33FC")
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Name(_CID, "INT33FC")
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Name(_UID, 3)
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Name(RBUF, ResourceTemplate()
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{
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Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
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Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
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{
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GPIO_SUS_IRQ
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}
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})
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Method(_CRS)
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{
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CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
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Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
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Return (^RBUF)
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}
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Method(_STA)
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{
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Return (STA_VISIBLE)
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}
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}
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