mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 18:41:03 +00:00
89 lines
3.9 KiB
C
89 lines
3.9 KiB
C
/*
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* SPORT Masks
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*/
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#ifndef __BFIN_PERIPHERAL_SPORT__
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#define __BFIN_PERIPHERAL_SPORT__
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/* SPORTx_TCR1 Masks */
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#define TSPEN 0x0001 /* TX enable */
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#define ITCLK 0x0002 /* Internal TX Clock Select */
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#define TDTYPE 0x000C /* TX Data Formatting Select */
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#define DTYPE_NORM 0x0004 /* Data Format Normal */
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#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
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#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
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#define TLSBIT 0x0010 /* TX Bit Order */
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#define ITFS 0x0200 /* Internal TX Frame Sync Select */
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#define TFSR 0x0400 /* TX Frame Sync Required Select */
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#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
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#define LTFS 0x1000 /* Low TX Frame Sync Select */
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#define LATFS 0x2000 /* Late TX Frame Sync Select */
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#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
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/* SPORTx_TCR2 Masks */
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#define SLEN 0x001F /* TX Word Length */
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#define TXSE 0x0100 /* TX Secondary Enable */
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#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */
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#define TRFST 0x0400 /* TX Right-First Data Order */
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/* SPORTx_RCR1 Masks */
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#define RSPEN 0x0001 /* RX enable */
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#define IRCLK 0x0002 /* Internal RX Clock Select */
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#define RDTYPE 0x000C /* RX Data Formatting Select */
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#define DTYPE_NORM 0x0004 /* Data Format Normal */
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#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
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#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
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#define RLSBIT 0x0010 /* RX Bit Order */
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#define IRFS 0x0200 /* Internal RX Frame Sync Select */
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#define RFSR 0x0400 /* RX Frame Sync Required Select */
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#define LRFS 0x1000 /* Low RX Frame Sync Select */
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#define LARFS 0x2000 /* Late RX Frame Sync Select */
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#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
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/* SPORTx_RCR2 Masks */
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#define SLEN 0x001F /* RX Word Length */
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#define RXSE 0x0100 /* RX Secondary Enable */
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#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
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#define RRFST 0x0400 /* Right-First Data Order */
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/* SPORTx_STAT Masks */
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#define RXNE 0x0001 /* RX FIFO Not Empty Status */
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#define RUVF 0x0002 /* RX Underflow Status */
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#define ROVF 0x0004 /* RX Overflow Status */
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#define TXF 0x0008 /* TX FIFO Full Status */
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#define TUVF 0x0010 /* TX Underflow Status */
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#define TOVF 0x0020 /* TX Overflow Status */
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#define TXHRE 0x0040 /* TX Hold Register Empty */
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/* SPORTx_MCMC1 Masks */
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#define WSIZE 0xF000 /* Multichannel Window Size Field */
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#define WOFF 0x03FF /* Multichannel Window Offset Field */
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/* SPORTx_MCMC2 Masks */
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#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
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#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
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#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
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#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
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#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
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#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
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#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
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#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
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#define MFD 0xF000 /* Multichannel Frame Delay */
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#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
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#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
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#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
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#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
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#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
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#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
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#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
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#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
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#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
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#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
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#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
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#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
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#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
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#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
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#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
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#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
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#endif
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